| Line 39... |
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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020006"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030000"; -- no touchy!
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
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constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
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constant gpio_size_c : natural := 2*4; -- bytes, fixed!
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constant gpio_size_c : natural := 2*4; -- bytes, fixed!
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constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
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constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
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constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
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constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
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-- Core-Local Interrupt Controller (CLIC) --
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-- RESERVED --
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constant clic_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
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--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
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constant clic_size_c : natural := 1*4; -- bytes, fixed!
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--constant ???_size_c : natural := 1*4; -- bytes, fixed!
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constant clic_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(clic_base_c) + x"00000000");
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-- Watch Dog Timer (WDT) --
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-- Watch Dog Timer (WDT) --
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_size_c : natural := 1*4; -- bytes, fixed!
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constant wdt_size_c : natural := 1*4; -- bytes, fixed!
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constant wdt_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"00000000");
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constant wdt_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"00000000");
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constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
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constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
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constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
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constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
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-- Trap ID Codes --------------------------------------------------------------------------
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-- Trap ID Codes --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned
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-- risc-v compliant --
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constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault
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constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
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constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction
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constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault
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constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint
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constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction
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constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned
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constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint
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constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault
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constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned
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constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned
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constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault
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constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault
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constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned
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constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode
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constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault
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constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt
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constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode
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constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt
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--
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constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt
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constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt
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constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt
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constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt
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-- custom --
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constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0
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constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1
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constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2
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constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3
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-- CPU Control Exception System -----------------------------------------------------------
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-- CPU Control Exception System -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- exception source bits --
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-- exception source bits --
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constant exception_iaccess_c : natural := 0; -- instrution access fault
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constant exception_iaccess_c : natural := 0; -- instrution access fault
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constant exception_break_c : natural := 4; -- breakpoint
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constant exception_break_c : natural := 4; -- breakpoint
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constant exception_salign_c : natural := 5; -- store address misaligned
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constant exception_salign_c : natural := 5; -- store address misaligned
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constant exception_lalign_c : natural := 6; -- load address misaligned
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constant exception_lalign_c : natural := 6; -- load address misaligned
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constant exception_saccess_c : natural := 7; -- store access fault
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constant exception_saccess_c : natural := 7; -- store access fault
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constant exception_laccess_c : natural := 8; -- load access fault
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constant exception_laccess_c : natural := 8; -- load access fault
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--
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constant exception_width_c : natural := 9; -- length of this list in bits
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constant exception_width_c : natural := 9; -- length of this list in bits
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-- interrupt source bits --
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-- interrupt source bits --
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constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
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constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
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constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
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constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
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constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
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constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
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constant interrupt_width_c : natural := 3; -- length of this list in bits
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constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
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constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
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constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
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constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
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--
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constant interrupt_width_c : natural := 7; -- length of this list in bits
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-- Clock Generator -------------------------------------------------------------------------
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-- Clock Generator -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant clk_div2_c : natural := 0;
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constant clk_div2_c : natural := 0;
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constant clk_div4_c : natural := 1;
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constant clk_div4_c : natural := 1;
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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uart_txd_o : out std_ulogic; -- UART send data
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uart_txd_o : out std_ulogic; -- UART send data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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-- SPI --
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-- SPI --
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
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spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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-- TWI --
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-- TWI --
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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-- PWM --
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-- PWM --
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pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
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pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
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-- Interrupts --
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-- Interrupts --
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ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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);
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);
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end component;
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end component;
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu
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component neorv32_cpu
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generic (
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generic (
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-- General --
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-- General --
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: External memory interface --
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-- Bus Interface --
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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-- instruction bus interface --
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-- instruction bus interface --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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-- data bus interface --
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- external interrupts --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
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);
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);
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end component;
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end component;
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-- Component: CPU Control -----------------------------------------------------------------
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-- Component: CPU Control -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 527... |
Line 540... |
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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-- csr interface --
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-- csr interface --
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- external interrupt --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- software interrupt
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msw_irq_i : in std_ulogic; -- machine software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0);
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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| Line 618... |
Line 633... |
-- Component: CPU Bus Interface -----------------------------------------------------------
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-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
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component neorv32_cpu_bus
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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| Line 819... |
Line 834... |
-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic
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irq_o : out std_ulogic
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);
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);
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end component;
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end component;
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-- Component: Core Local Interrupt Controller (CLIC) --------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_clic
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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-- cpu interrupt --
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cpu_irq_o : out std_ulogic; -- trigger CPU's external IRQ
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-- external interrupt lines --
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ext_irq_i : in std_ulogic_vector(07 downto 0); -- IRQ, triggering on HIGH level
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ext_ack_o : out std_ulogic_vector(07 downto 0) -- acknowledge
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);
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end component;
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-- Component: Watchdog Timer (WDT) --------------------------------------------------------
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-- Component: Watchdog Timer (WDT) --------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_wdt
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component neorv32_wdt
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port (
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port (
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-- host access --
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-- host access --
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| Line 1062... |
Line 1056... |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- host access --
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-- host access --
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