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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030500"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030501"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions
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constant pmp_max_r_c : natural := 8; -- max PMP regions
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Bus Interface --
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-- Bus Interface --
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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firq_i : in std_ulogic_vector(3 downto 0);
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firq_i : in std_ulogic_vector(3 downto 0);
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_maddr_i : in pmp_addr_if_t; -- masked addresses
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
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priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_maddr_o : out pmp_addr_if_t; -- masked addresses
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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