| Line 39... |
Line 39... |
package neorv32_package is
|
package neorv32_package is
|
|
|
-- Architecture Constants -----------------------------------------------------------------
|
-- Architecture Constants -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040402"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040405"; -- no touchy!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
|
|
-- Architecture Configuration -------------------------------------------------------------
|
-- Architecture Configuration -------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory address space base address
|
|
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and triggers an access exception
|
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
|
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 92... |
Line 93... |
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
|
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
|
constant gpio_size_c : natural := 2*4; -- bytes
|
constant gpio_size_c : natural := 2*4; -- bytes
|
constant gpio_in_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
|
constant gpio_in_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
|
constant gpio_out_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
|
constant gpio_out_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
|
|
|
-- Dummy Device (with SIMULATION output) (DEVNULL) --
|
-- True Random Number Generator (TRNG) --
|
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
|
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
|
constant devnull_size_c : natural := 1*4; -- bytes
|
constant trng_size_c : natural := 1*4; -- bytes
|
constant devnull_data_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
|
constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
|
|
|
-- Watch Dog Timer (WDT) --
|
-- Watch Dog Timer (WDT) --
|
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
|
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
|
constant wdt_size_c : natural := 1*4; -- bytes
|
constant wdt_size_c : natural := 1*4; -- bytes
|
constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
|
constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
|
| Line 134... |
Line 135... |
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
|
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
|
constant pwm_size_c : natural := 2*4; -- bytes
|
constant pwm_size_c : natural := 2*4; -- bytes
|
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
|
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
|
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
|
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
|
|
|
-- True Random Number Generator (TRNG) --
|
|
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
|
|
constant trng_size_c : natural := 1*4; -- bytes
|
|
constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
|
|
|
|
-- RESERVED --
|
-- RESERVED --
|
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4"; -- base address, fixed!
|
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
|
--constant ???_size_c : natural := 3*4; -- bytes
|
--constant ???_size_c : natural := 4*4; -- bytes
|
|
|
-- Custom Functions Unit (CFU) --
|
-- Custom Functions Unit (CFU) --
|
constant cfu_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
|
constant cfu_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
|
constant cfu_size_c : natural := 4*4; -- bytes
|
constant cfu_size_c : natural := 4*4; -- bytes
|
constant cfu_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
|
constant cfu_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
|
| Line 176... |
Line 172... |
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
|
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
|
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
|
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
|
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
|
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
|
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
|
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
|
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
|
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
|
constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero), also forces dst=r0
|
constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero)
|
-- alu --
|
-- alu --
|
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
|
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
|
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
|
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
|
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
|
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
| Line 469... |
Line 465... |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true; -- implement dummy device (DEVNULL)?
|
|
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
|
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
| Line 540... |
Line 534... |
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Bus Interface --
|
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 720... |
Line 712... |
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
BUS_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
|
PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
|
PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
|
);
|
);
|
| Line 1098... |
Line 1089... |
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Dummy Device with SIM Output (DEVNULL) --------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_devnull
|
|
port (
|
|
-- host access --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
rden_i : in std_ulogic; -- read enable
|
|
wren_i : in std_ulogic; -- write enable
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
|
);
|
|
end component;
|
|
|
|
-- Component: Custom Functions Unit (CFU) -------------------------------------------------
|
-- Component: Custom Functions Unit (CFU) -------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cfu
|
component neorv32_cfu
|
port (
|
port (
|
-- host access --
|
-- host access --
|
| Line 1162... |
Line 1138... |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true; -- implement dummy device (DEVNULL)?
|
|
IO_CFU_USE : boolean := true -- implement custom functions unit (CFU)?
|
IO_CFU_USE : boolean := true -- implement custom functions unit (CFU)?
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
