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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - do not change!
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constant data_width_c : natural := 32; -- data width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040502"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040509"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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-- Architecture Configuration -------------------------------------------------------------
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-- Architecture Configuration -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Internal Instruction Memory (IMEM) --
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-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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--> size is configured via top's generic
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-- Internal Data Memory (DMEM) --
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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--> size is configured via top's generic
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--> sizea are configured via top's generic
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-- Internal Bootloader ROM --
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-- Internal Bootloader ROM --
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_size_c : natural := 4*1024; -- bytes
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constant boot_rom_size_c : natural := 4*1024; -- bytes
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constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
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constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
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constant pwm_size_c : natural := 2*4; -- bytes
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constant pwm_size_c : natural := 2*4; -- bytes
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constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
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constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
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constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
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constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
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-- RESERVED --
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-- Custom Functions Unit 0 (CFU0) --
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--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
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constant cfu0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
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--constant ???_size_c : natural := 4*4; -- bytes
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constant cfu0_size_c : natural := 4*4; -- bytes
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constant cfu0_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
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-- Custom Functions Unit (CFU) --
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constant cfu0_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
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constant cfu_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
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constant cfu0_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
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constant cfu_size_c : natural := 4*4; -- bytes
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constant cfu0_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
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constant cfu_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
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constant cfu_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
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-- Custom Functions Unit 1 (CFU1) --
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constant cfu_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
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constant cfu1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
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constant cfu_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
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constant cfu1_size_c : natural := 4*4; -- bytes
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constant cfu1_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
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constant cfu1_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
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constant cfu1_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
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constant cfu1_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
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-- System Information Memory (SYSINFO) --
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-- System Information Memory (SYSINFO) --
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constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
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constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
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constant sysinfo_size_c : natural := 8*4; -- bytes
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constant sysinfo_size_c : natural := 8*4; -- bytes
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
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IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
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IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
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IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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Line 516... |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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-- PWM --
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-- PWM --
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pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
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pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
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-- Interrupts --
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-- Interrupts --
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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);
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);
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end component;
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end component;
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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);
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);
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Line 667... |
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_alu
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component neorv32_cpu_alu
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generic (
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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Line 1099... |
wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_err_i : in std_ulogic -- transfer error
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wb_err_i : in std_ulogic -- transfer error
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);
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);
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end component;
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end component;
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-- Component: Custom Functions Unit (CFU) -------------------------------------------------
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-- Component: Custom Functions Unit 0 (CFU0) ----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cfu
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component neorv32_cfu0
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, use as async
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rstn_i : in std_ulogic; -- global reset line, low-active, use as async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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| Line 1108... |
Line 1114... |
data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
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clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
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-- interrupt --
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-- custom io --
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irq_o : out std_ulogic
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-- ...
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);
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end component;
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-- Component: Custom Functions Unit 1 (CFU1) ----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cfu1
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, use as async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
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-- custom io --
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-- custom io --
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-- ...
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-- ...
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);
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);
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end component;
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end component;
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Line 1167... |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_CFU_USE : boolean := true -- implement custom functions unit (CFU)?
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IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)?
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IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)?
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);
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);
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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