| Line 36... |
Line 36... |
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
package neorv32_package is
|
package neorv32_package is
|
|
|
|
-- Architecture Configuration -------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and trigger an access exception
|
|
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
|
|
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
|
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
|
|
|
-- Architecture Constants -----------------------------------------------------------------
|
-- Architecture Constants -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040600"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040606"; -- no touchy!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- Architecture Configuration -------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory address space base address
|
|
constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory address space base address
|
|
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and triggers an access exception
|
|
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode (better timing)
|
|
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
|
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
|
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural;
|
function index_size_f(input : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
| Line 64... |
Line 64... |
function and_all_f(a : std_ulogic_vector) return std_ulogic;
|
function and_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
|
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
|
|
function is_power_of_two_f(input : natural) return boolean;
|
|
|
-- Internal Types -------------------------------------------------------------------------
|
-- Internal Types -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
|
type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
|
type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
|
type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
|
| Line 176... |
Line 177... |
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
|
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
|
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
|
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
|
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
|
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
|
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
|
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
|
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
|
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
|
constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero)
|
constant ctrl_rf_r0_we_c : natural := 18; -- force write access and force rd=r0
|
-- alu --
|
-- alu --
|
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
|
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
|
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
|
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
|
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
|
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
| Line 204... |
Line 205... |
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
|
-- co-processors --
|
-- co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb
|
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb
|
constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb
|
constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb
|
constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0
|
-- current privilege level --
|
constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1
|
constant ctrl_priv_lvl_lsb_c : natural := 43; -- privilege level lsb
|
constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2
|
constant ctrl_priv_lvl_msb_c : natural := 44; -- privilege level msb
|
|
-- instruction's control blocks --
|
|
constant ctrl_ir_funct3_0_c : natural := 45; -- funct3 bit 0
|
|
constant ctrl_ir_funct3_1_c : natural := 46; -- funct3 bit 1
|
|
constant ctrl_ir_funct3_2_c : natural := 47; -- funct3 bit 2
|
|
constant ctrl_ir_funct12_0_c : natural := 48; -- funct12 bit 0
|
|
constant ctrl_ir_funct12_1_c : natural := 49; -- funct12 bit 1
|
|
constant ctrl_ir_funct12_2_c : natural := 50; -- funct12 bit 2
|
|
constant ctrl_ir_funct12_3_c : natural := 51; -- funct12 bit 3
|
|
constant ctrl_ir_funct12_4_c : natural := 52; -- funct12 bit 4
|
|
constant ctrl_ir_funct12_5_c : natural := 53; -- funct12 bit 5
|
|
constant ctrl_ir_funct12_6_c : natural := 54; -- funct12 bit 6
|
|
constant ctrl_ir_funct12_7_c : natural := 55; -- funct12 bit 7
|
|
constant ctrl_ir_funct12_8_c : natural := 56; -- funct12 bit 8
|
|
constant ctrl_ir_funct12_9_c : natural := 57; -- funct12 bit 9
|
|
constant ctrl_ir_funct12_10_c : natural := 58; -- funct12 bit 10
|
|
constant ctrl_ir_funct12_11_c : natural := 59; -- funct12 bit 11
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 46; -- control bus size
|
constant ctrl_width_c : natural := 60; -- control bus size
|
|
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 348... |
Line 365... |
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid
|
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid
|
--
|
--
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (custom)
|
|
|
-- Co-Processor Operations ----------------------------------------------------------------
|
-- Co-Processor Operations ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- cp ids --
|
-- cp ids --
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV
|
|
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "01"; -- BITMANIP
|
|
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved
|
|
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved
|
-- muldiv cp --
|
-- muldiv cp --
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
| Line 446... |
Line 466... |
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
| Line 486... |
Line 507... |
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface --
|
-- Wishbone bus interface --
|
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
priv_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO --
|
-- GPIO --
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
| Line 614... |
Line 635... |
bus_i_wait_i : in std_ulogic; -- wait for bus
|
bus_i_wait_i : in std_ulogic; -- wait for bus
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
-- data input --
|
-- data input --
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
|
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
-- data output --
|
-- data output --
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
| Line 632... |
Line 654... |
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
|
-- bus access exceptions --
|
-- bus access exceptions --
|
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
|
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
| Line 685... |
Line 706... |
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
-- data output --
|
-- data output --
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
|
opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B
|
-- co-processor interface --
|
-- co-processor interface --
|
cp0_start_o : out std_ulogic; -- trigger co-processor 0
|
cp0_start_o : out std_ulogic; -- trigger co-processor 0
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
|
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
|
cp1_start_o : out std_ulogic; -- trigger co-processor 1
|
cp1_start_o : out std_ulogic; -- trigger co-processor 1
|
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
|
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
|
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
|
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
|
|
cp2_start_o : out std_ulogic; -- trigger co-processor 2
|
|
cp2_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
|
|
cp2_valid_i : in std_ulogic; -- co-processor 2 result valid
|
|
cp3_start_o : out std_ulogic; -- trigger co-processor 3
|
|
cp3_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
|
|
cp3_valid_i : in std_ulogic; -- co-processor 3 result valid
|
-- status --
|
-- status --
|
wait_o : out std_ulogic -- busy due to iterative processing units
|
wait_o : out std_ulogic -- busy due to iterative processing units
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 708... |
Line 737... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
|
start_i : in std_ulogic; -- trigger operation
|
start_i : in std_ulogic; -- trigger operation
|
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
| Line 731... |
Line 760... |
PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
|
PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- cpu instruction fetch interface --
|
-- cpu instruction fetch interface --
|
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
i_wait_o : out std_ulogic; -- wait for fetch to complete
|
i_wait_o : out std_ulogic; -- wait for fetch to complete
|
| Line 754... |
Line 782... |
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_i : in pmp_addr_if_t; -- addresses
|
pmp_addr_i : in pmp_addr_if_t; -- addresses
|
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
|
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
|
priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
|
-- instruction bus --
|
-- instruction bus --
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 812... |
Line 839... |
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
| Line 1078... |
Line 1106... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
-- host access --
|
-- host access --
|
|
src_i : in std_ulogic; -- access type (0: data, 1:instruction)
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
|
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
|
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1324... |
Line 1355... |
output_v(input'length-i-1) := input(i);
|
output_v(input'length-i-1) := input(i);
|
end loop; -- i
|
end loop; -- i
|
return output_v;
|
return output_v;
|
end function bit_rev_f;
|
end function bit_rev_f;
|
|
|
|
-- Function: Test if input number is a power of two ---------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
function is_power_of_two_f(input : natural) return boolean is
|
|
begin
|
|
if ((input / 2) /= 0) and ((input mod 2) = 0) then
|
|
return true;
|
|
else
|
|
return false;
|
|
end if;
|
|
end function is_power_of_two_f;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
No newline at end of file
|
No newline at end of file
|
