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-- Architecture Configuration -------------------------------------------------------------
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-- Architecture Configuration -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
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constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
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constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
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constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
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constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and trigger an access exception
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constant bus_timeout_c : natural := 127; -- cycles after which an *unacknwoledged* bus access will timeout and trigger an access exception
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constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - do not change!
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constant data_width_c : natural := 32; -- data width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040700"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040702"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
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PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- cpu instruction fetch interface --
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-- cpu instruction fetch interface --
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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port (
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port (
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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upen_i : in std_ulogic; -- update enable
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic -- transfer acknowledge
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ack_o : out std_ulogic -- transfer acknowledge
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);
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);
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-- Function: Test if input number is a power of two ---------------------------------------
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-- Function: Test if input number is a power of two ---------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function is_power_of_two_f(input : natural) return boolean is
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function is_power_of_two_f(input : natural) return boolean is
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begin
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begin
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if ((input / 2) /= 0) and ((input mod 2) = 0) then
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if (input = 1) then -- 2^0
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return true;
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elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
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return true;
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return true;
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else
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else
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return false;
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return false;
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end if;
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end if;
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end function is_power_of_two_f;
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end function is_power_of_two_f;
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