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-- Architecture Configuration -------------------------------------------------------------
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-- Architecture Configuration -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
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constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
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constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
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constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
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constant bus_timeout_c : natural := 127; -- cycles after which an *unacknwoledged* bus access will timeout and trigger an access exception
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constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger an access exception
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constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - do not change!
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constant data_width_c : natural := 32; -- data width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040702"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040801"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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|
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
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-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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--> sizea are configured via top's generic
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--> memory sizes are configured via top's generics
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|
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-- Internal Bootloader ROM --
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-- Internal Bootloader ROM --
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_size_c : natural := 4*1024; -- bytes
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constant boot_rom_size_c : natural := 4*1024; -- bytes
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constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant sysinfo_size_c : natural := 8*4; -- bytes
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constant sysinfo_size_c : natural := 8*4; -- bytes
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-- Main Control Bus -----------------------------------------------------------------------
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-- Main Control Bus -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- register file --
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-- register file --
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constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
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constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (10=MEM, 11=CSR)
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constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
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constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (0-=ALU)
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constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0
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constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0
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constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1
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constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1
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constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2
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constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2
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constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3
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constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3
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constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4
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constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4
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constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
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constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
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constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
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constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
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constant ctrl_rf_r0_we_c : natural := 18; -- force write access and force rd=r0
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constant ctrl_rf_r0_we_c : natural := 18; -- force write access and force rd=r0
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-- alu --
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-- alu --
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constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
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constant ctrl_alu_arith_c : natural := 19; -- ALU arithmetic command
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constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
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constant ctrl_alu_logic0_c : natural := 20; -- ALU logic command bit 0
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constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
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constant ctrl_alu_logic1_c : natural := 21; -- ALU logic command bit 1
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constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
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constant ctrl_alu_func0_c : natural := 22; -- ALU function select command bit 0
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constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC)
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constant ctrl_alu_func1_c : natural := 23; -- ALU function select command bit 1
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constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM)
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constant ctrl_alu_addsub_c : natural := 24; -- 0=ADD, 1=SUB
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constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation
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constant ctrl_alu_opa_mux_c : natural := 25; -- operand A select (0=rs1, 1=PC)
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constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right)
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constant ctrl_alu_opb_mux_c : natural := 26; -- operand B select (0=rs2, 1=IMM)
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constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift
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constant ctrl_alu_unsigned_c : natural := 27; -- is unsigned ALU operation
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constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_ar_c : natural := 29; -- is arithmetic shift
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-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 28; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_msb_c : natural := 29; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_rd_c : natural := 30; -- read data request
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constant ctrl_bus_rd_c : natural := 32; -- read data request
|
constant ctrl_bus_wr_c : natural := 31; -- write data request
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constant ctrl_bus_wr_c : natural := 33; -- write data request
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constant ctrl_bus_if_c : natural := 32; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 34; -- instruction fetch request
|
constant ctrl_bus_mar_we_c : natural := 33; -- memory address register write enable
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constant ctrl_bus_mo_we_c : natural := 35; -- memory address and data output register write enable
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constant ctrl_bus_mdo_we_c : natural := 34; -- memory data out register write enable
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constant ctrl_bus_mi_we_c : natural := 36; -- memory data input register write enable
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constant ctrl_bus_mdi_we_c : natural := 35; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load
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constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
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constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions
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constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions
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constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions
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constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions
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constant ctrl_bus_fence_c : natural := 40; -- executed fence operation
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constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
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constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation
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constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
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constant ctrl_bus_lock_c : natural := 42; -- locked/exclusive bus access
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-- co-processors --
|
-- co-processors --
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constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb
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constant ctrl_cp_id_lsb_c : natural := 43; -- cp select ID lsb
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constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb
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constant ctrl_cp_id_msb_c : natural := 44; -- cp select ID msb
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-- current privilege level --
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-- current privilege level --
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constant ctrl_priv_lvl_lsb_c : natural := 43; -- privilege level lsb
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constant ctrl_priv_lvl_lsb_c : natural := 45; -- privilege level lsb
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constant ctrl_priv_lvl_msb_c : natural := 44; -- privilege level msb
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constant ctrl_priv_lvl_msb_c : natural := 46; -- privilege level msb
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-- instruction's control blocks --
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-- instruction's control blocks --
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constant ctrl_ir_funct3_0_c : natural := 45; -- funct3 bit 0
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constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
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constant ctrl_ir_funct3_1_c : natural := 46; -- funct3 bit 1
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constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
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constant ctrl_ir_funct3_2_c : natural := 47; -- funct3 bit 2
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constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
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constant ctrl_ir_funct12_0_c : natural := 48; -- funct12 bit 0
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constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
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constant ctrl_ir_funct12_1_c : natural := 49; -- funct12 bit 1
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constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1
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constant ctrl_ir_funct12_2_c : natural := 50; -- funct12 bit 2
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constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2
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constant ctrl_ir_funct12_3_c : natural := 51; -- funct12 bit 3
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constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3
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constant ctrl_ir_funct12_4_c : natural := 52; -- funct12 bit 4
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constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4
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constant ctrl_ir_funct12_5_c : natural := 53; -- funct12 bit 5
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constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5
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constant ctrl_ir_funct12_6_c : natural := 54; -- funct12 bit 6
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constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6
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constant ctrl_ir_funct12_7_c : natural := 55; -- funct12 bit 7
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constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7
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constant ctrl_ir_funct12_8_c : natural := 56; -- funct12 bit 8
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constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8
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constant ctrl_ir_funct12_9_c : natural := 57; -- funct12 bit 9
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constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9
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constant ctrl_ir_funct12_10_c : natural := 58; -- funct12 bit 10
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constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
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constant ctrl_ir_funct12_11_c : natural := 59; -- funct12 bit 11
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constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
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-- control bus size --
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-- control bus size --
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constant ctrl_width_c : natural := 60; -- control bus size
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constant ctrl_width_c : natural := 62; -- control bus size
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|
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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| Line 254... |
Line 256... |
constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
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constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
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constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
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constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
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constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
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constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
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constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
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constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
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constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
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constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
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constant instr_funct5_lsb_c : natural := 27; -- funct5 select bit 0
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constant instr_funct5_msb_c : natural := 31; -- funct5 select bit 4
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|
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-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- alu --
|
-- alu --
|
constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
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constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
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| Line 272... |
Line 276... |
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
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constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
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constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
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constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
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-- system/csr --
|
-- system/csr --
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constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
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constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
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constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
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constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
|
-- atomic operations (A) --
|
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- control flow --
|
-- control flow --
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
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constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
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| Line 313... |
Line 319... |
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
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constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
-- fence --
|
-- fence --
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
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constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
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|
|
-- RISC-V Funct12 --------------------------------------------------------------------------
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-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
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constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
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constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
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constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
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constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
|
|
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
-- atomic operations --
|
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
|
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
|
|
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus
|
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus
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constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa
|
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie
|
| Line 371... |
Line 383... |
|
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-- Co-Processor Operations ----------------------------------------------------------------
|
-- Co-Processor Operations ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- cp ids --
|
-- cp ids --
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV
|
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "01"; -- BITMANIP
|
constant cp_sel_atomic_c : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations success/failure evaluation
|
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved
|
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved
|
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved
|
-- muldiv cp --
|
-- muldiv cp --
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
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constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
| Line 386... |
Line 398... |
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
|
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
|
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
|
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmd_addsub_c : std_ulogic_vector(2 downto 0) := "000"; -- r <= A +/- B
|
-- arithmetic core --
|
constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "001"; -- r <= A < B
|
constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
|
constant alu_cmd_cp_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= CP result (iterative)
|
constant alu_arith_cmd_slt_c : std_ulogic := '1'; -- r.arith <= A < B
|
constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B (iterative)
|
-- logic core --
|
constant alu_cmd_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= B
|
constant alu_logic_cmd_movb_c : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
|
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A xor B
|
constant alu_logic_cmd_xor_c : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A or B
|
constant alu_logic_cmd_or_c : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and B
|
constant alu_logic_cmd_and_c : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
|
|
-- function select (actual alu result) --
|
|
constant alu_func_cmd_arith_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
|
|
constant alu_func_cmd_logic_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
|
|
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
|
|
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- risc-v compliant --
|
-- RISC-V compliant exceptions --
|
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
|
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0: instruction misaligned
|
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault
|
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1: instruction access fault
|
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction
|
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2: illegal instruction
|
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint
|
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3: breakpoint
|
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned
|
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4: load address misaligned
|
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault
|
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5: load access fault
|
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned
|
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned
|
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault
|
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault
|
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode
|
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
|
--
|
-- RISC-V compliant interrupts --
|
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt
|
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
|
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt
|
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt
|
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
|
-- custom --
|
-- NEORV32-specific (custom) interrupts --
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
| Line 447... |
Line 464... |
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
|
|
-- Clock Generator -------------------------------------------------------------------------
|
-- Clock Generator ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant clk_div2_c : natural := 0;
|
constant clk_div2_c : natural := 0;
|
constant clk_div4_c : natural := 1;
|
constant clk_div4_c : natural := 1;
|
constant clk_div8_c : natural := 2;
|
constant clk_div8_c : natural := 2;
|
constant clk_div64_c : natural := 3;
|
constant clk_div64_c : natural := 3;
|
| Line 468... |
Line 485... |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
| Line 515... |
Line 533... |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
| Line 551... |
Line 570... |
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
| Line 581... |
Line 601... |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 593... |
Line 614... |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
|
d_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
| Line 612... |
Line 634... |
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
| Line 641... |
Line 664... |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
-- data output --
|
-- data output --
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
| Line 679... |
Line 701... |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc
|
|
-- data output --
|
-- data output --
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
);
|
);
|
end component;
|
end component;
|
| Line 794... |
Line 815... |
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic -- fence operation
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
|
d_bus_lock_o : out std_ulogic -- locked/exclusive access
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 827... |
Line 850... |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
ca_bus_lock_i : in std_ulogic; -- locked/exclusive access
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
-- controller interface b --
|
-- controller interface b --
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
cb_bus_lock_i : in std_ulogic; -- locked/exclusive access
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
| Line 848... |
Line 873... |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
p_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1114... |
Line 1140... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
lock_i : in std_ulogic; -- locked/exclusive bus access
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
|
| Line 1126... |
Line 1153... |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
