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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000204"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000206"; -- no touchy!
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-- Internal Functions ---------------------------------------------------------------------
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-- Internal Functions ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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-- bus interface --
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-- bus interface --
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constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_rd_c : natural := 33; -- read data request
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constant ctrl_bus_rd_c : natural := 33; -- read data request
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constant ctrl_bus_wr_c : natural := 34; -- write data request
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constant ctrl_bus_wr_c : natural := 34; -- write data request
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (output PC, otherwise output MAR)
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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-- csr/system --
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-- csr/system --
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ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
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ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
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ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
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ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
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);
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);
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end component;
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end component;
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu
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generic (
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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-- external interrupts --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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end component;
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-- Component: CPU Control -----------------------------------------------------------------
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-- Component: CPU Control -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_control
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component neorv32_cpu_control
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generic (
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generic (
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-- General --
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-- General --
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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);
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);
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end component;
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end component;
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu
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generic (
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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-- external interrupts --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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end component;
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-- Component: Processor-internal instruction memory (IMEM) --------------------------------
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-- Component: Processor-internal instruction memory (IMEM) --------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_imem
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component neorv32_imem
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generic (
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generic (
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IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
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IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_mtime
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component neorv32_mtime
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_err_i : in std_ulogic -- transfer error
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wb_err_i : in std_ulogic -- transfer error
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);
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);
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end component;
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end component;
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-- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
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---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
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-- -------------------------------------------------------------------------------------------
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---- -------------------------------------------------------------------------------------------
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component neorv32_devnull
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component neorv32_devnull
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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