| Line 43... |
Line 43... |
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- (external) bus interface --
|
-- (external) bus interface --
|
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus access exception (min 3)
|
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
|
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
|
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
|
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
|
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
|
|
|
-- CPU core --
|
-- CPU core --
|
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, must be a power of 2, default=2
|
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
|
constant zicnt_en_c : boolean := true; -- enable RISC-V performance counters ([m]cycle[h], [m]instret[h]), default=true
|
|
|
|
-- physical memory protection (PMP) --
|
-- physical memory protection (PMP) --
|
constant pmp_num_regions_c : natural := 2; -- number of regions (1..8)
|
constant pmp_num_regions_c : natural := 2; -- number of regions (1..8)
|
constant pmp_min_granularity_c : natural := 64*1024; -- minimal region size (granularity), min 8 bytes, has to be a power of 2
|
constant pmp_min_granularity_c : natural := 64*1024; -- minimal region size (granularity), min 8 bytes, has to be a power of 2
|
|
|
-- Architecture Constants (do not modify!)= -----------------------------------------------
|
-- Architecture Constants (do not modify!)= -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant data_width_c : natural := 32; -- data width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040900"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040904"; -- no touchy!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the HW
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the HW
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
| Line 348... |
Line 347... |
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
|
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
|
|
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
-- read/write CSRs --
|
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus
|
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus
|
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa
|
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie
|
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec
|
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec
|
|
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306"; -- mcounteren
|
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; -- mstatush
|
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; -- mstatush
|
--
|
--
|
|
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320"; -- mcountinhibit
|
|
--
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip
|
| Line 377... |
Line 380... |
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle
|
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle
|
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret
|
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret
|
--
|
--
|
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh
|
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh
|
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth
|
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth
|
--
|
-- read-only CSRs --
|
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle
|
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle
|
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time
|
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time
|
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret
|
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret
|
--
|
--
|
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh
|
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh
|
| Line 521... |
Line 524... |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
|
-- Internal Cache memory --
|
|
ICACHE_USE : boolean := false; -- implement instruction cache
|
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
| Line 586... |
Line 593... |
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
|
|
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
| Line 787... |
Line 795... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_USE : boolean := false -- implement physical memory protection?
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
|
-- Bus Timeout --
|
|
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 842... |
Line 852... |
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_lock_o : out std_ulogic -- locked/exclusive access
|
d_bus_lock_o : out std_ulogic -- locked/exclusive access
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Component: CPU Cache -------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_cache
|
|
generic (
|
|
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
|
|
CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
|
clear_i : in std_ulogic; -- cache clear
|
|
-- host controller interface --
|
|
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
|
host_we_i : in std_ulogic; -- write enable
|
|
host_re_i : in std_ulogic; -- read enable
|
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
host_lock_i : in std_ulogic; -- locked/exclusive access
|
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
|
host_err_o : out std_ulogic; -- bus transfer error
|
|
-- peripheral bus interface --
|
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
bus_we_o : out std_ulogic; -- write enable
|
|
bus_re_o : out std_ulogic; -- read enable
|
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
bus_err_i : in std_ulogic -- bus transfer error
|
|
);
|
|
end component;
|
|
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_busswitch
|
component neorv32_busswitch
|
generic (
|
generic (
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
| Line 1227... |
Line 1274... |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Internal Cache memory --
|
|
ICACHE_USE : boolean := true; -- implement instruction cache
|
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
|
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
| Line 1255... |
Line 1307... |
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
package body neorv32_package is
|
package body neorv32_package is
|
|
|
-- Function: Minimal required bit width ---------------------------------------------------
|
-- Function: Minimal required number of bits to represent input number --------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural is
|
function index_size_f(input : natural) return natural is
|
begin
|
begin
|
for i in 0 to natural'high loop
|
for i in 0 to natural'high loop
|
if (2**i >= input) then
|
if (2**i >= input) then
|
