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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Diff between revs 48 and 49

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Rev 48 Rev 49
Line 58... Line 58... 
  constant pmp_num_regions_critical_c : natural := 8;
 
  constant pmp_num_regions_critical_c : natural := 8;
 
 
 
 
 
  -- Architecture Constants (do not modify!) ------------------------------------------------
 
  -- Architecture Constants (do not modify!) ------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050100"; -- no touchy!
 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050104"; -- no touchy!
 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
 
 
 
 
 
  -- Helper Functions -----------------------------------------------------------------------
 
  -- Helper Functions -----------------------------------------------------------------------
Line 83... Line 83... 
 
 
 
 
  -- Internal Types -------------------------------------------------------------------------
 
  -- Internal Types -------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
 
 
 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
 
 
 
 
 
  -- Processor-Internal Address Space Layout ------------------------------------------------
 
  -- Processor-Internal Address Space Layout ------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
Line 185... Line 186... 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
 
 
 
 
 
 
 
  -- Numerically-Controlled Oscillator (NCO) --
 
 
 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
 
 
 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
 
 
 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
 
 
 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
 
 
 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
 
 
 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
 
 
 
 
 
  -- reserved --
 
  -- reserved --
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
 
--constant reserved_size_c      : natural := 8*4; -- module's address space in bytes
 
--constant reserved_size_c      : natural := 4*4; -- module's address space in bytes
 
 
 
 
 
  -- System Information Memory (SYSINFO) --
 
  -- System Information Memory (SYSINFO) --
 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
 
 
 
 
 
  -- Main Control Bus -----------------------------------------------------------------------
 
  -- Main Control Bus -----------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- register file --
 
  -- register file --
 
  constant ctrl_rf_in_mux_lsb_c : natural :=  0; -- input source select lsb (10=MEM, 11=CSR)
 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
 
  constant ctrl_rf_in_mux_msb_c : natural :=  1; -- input source select msb (0-=ALU)
 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
 
  constant ctrl_rf_rs1_adr0_c   : natural :=  2; -- source register 1 address bit 0
 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
 
  constant ctrl_rf_rs1_adr1_c   : natural :=  3; -- source register 1 address bit 1
 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
 
  constant ctrl_rf_rs1_adr2_c   : natural :=  4; -- source register 1 address bit 2
 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
 
  constant ctrl_rf_rs1_adr3_c   : natural :=  5; -- source register 1 address bit 3
 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
 
  constant ctrl_rf_rs1_adr4_c   : natural :=  6; -- source register 1 address bit 4
 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
 
  constant ctrl_rf_rs2_adr0_c   : natural :=  7; -- source register 2 address bit 0
 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
 
  constant ctrl_rf_rs2_adr1_c   : natural :=  8; -- source register 2 address bit 1
 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
 
  constant ctrl_rf_rs2_adr2_c   : natural :=  9; -- source register 2 address bit 2
 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
 
  constant ctrl_rf_rs2_adr3_c   : natural := 10; -- source register 2 address bit 3
 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
 
  constant ctrl_rf_rs2_adr4_c   : natural := 11; -- source register 2 address bit 4
 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
 
  constant ctrl_rf_rd_adr0_c    : natural := 12; -- destiantion register address bit 0
 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
 
  constant ctrl_rf_rd_adr1_c    : natural := 13; -- destiantion register address bit 1
 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
 
  constant ctrl_rf_rd_adr2_c    : natural := 14; -- destiantion register address bit 2
 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
 
  constant ctrl_rf_rd_adr3_c    : natural := 15; -- destiantion register address bit 3
 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
 
  constant ctrl_rf_rd_adr4_c    : natural := 16; -- destiantion register address bit 4
 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
 
  constant ctrl_rf_wb_en_c      : natural := 17; -- write back enable
 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
 
  constant ctrl_rf_r0_we_c      : natural := 18; -- force write access and force rd=r0
 
 
 
  -- alu --
 
  -- alu --
 
  constant ctrl_alu_arith_c     : natural := 19; -- ALU arithmetic command
 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
 
  constant ctrl_alu_logic0_c    : natural := 20; -- ALU logic command bit 0
 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
 
  constant ctrl_alu_logic1_c    : natural := 21; -- ALU logic command bit 1
 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
 
  constant ctrl_alu_func0_c     : natural := 22; -- ALU function select command bit 0
 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
 
  constant ctrl_alu_func1_c     : natural := 23; -- ALU function select command bit 1
 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
 
  constant ctrl_alu_addsub_c    : natural := 24; -- 0=ADD, 1=SUB
 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
 
  constant ctrl_alu_opa_mux_c   : natural := 25; -- operand A select (0=rs1, 1=PC)
 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
 
  constant ctrl_alu_opb_mux_c   : natural := 26; -- operand B select (0=rs2, 1=IMM)
 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
 
  constant ctrl_alu_unsigned_c  : natural := 27; -- is unsigned ALU operation
 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
 
  constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)
 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
 
  constant ctrl_alu_shift_ar_c  : natural := 29; -- is arithmetic shift
 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
 
  -- bus interface --
 
  -- bus interface --
 
  constant ctrl_bus_size_lsb_c  : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
 
  constant ctrl_bus_size_msb_c  : natural := 31; -- transfer size msb (10=word, 11=?)
 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
 
  constant ctrl_bus_rd_c        : natural := 32; -- read data request
 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
 
  constant ctrl_bus_wr_c        : natural := 33; -- write data request
 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
 
  constant ctrl_bus_if_c        : natural := 34; -- instruction fetch request
 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
 
  constant ctrl_bus_mo_we_c     : natural := 35; -- memory address and data output register write enable
 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
 
  constant ctrl_bus_mi_we_c     : natural := 36; -- memory data input register write enable
 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
 
  constant ctrl_bus_unsigned_c  : natural := 37; -- is unsigned load
 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
 
  constant ctrl_bus_ierr_ack_c  : natural := 38; -- acknowledge instruction fetch bus exceptions
 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
 
  constant ctrl_bus_derr_ack_c  : natural := 39; -- acknowledge data access bus exceptions
 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
 
  constant ctrl_bus_fence_c     : natural := 40; -- executed fence operation
 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
 
  constant ctrl_bus_fencei_c    : natural := 41; -- executed fencei operation
 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
 
  constant ctrl_bus_lock_c      : natural := 42; -- locked/exclusive bus access
 
  constant ctrl_bus_lock_c      : natural := 41; -- locked/exclusive bus access
 
  -- co-processors --
 
  -- co-processors --
 
  constant ctrl_cp_id_lsb_c     : natural := 43; -- cp select ID lsb
 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
 
 
 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID hsb
 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
 
  -- current privilege level --
 
  -- current privilege level --
 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
 
  -- instruction's control blocks (used by cpu co-processors) --
 
  -- instruction's control blocks (used by cpu co-processors) --
Line 653... Line 662... 
  -- custom read-only CSRs --
 
  -- custom read-only CSRs --
 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
 
 
 
 
 
  -- Co-Processor IDs -----------------------------------------------------------------------
 
  -- Co-Processor IDs -----------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  constant cp_sel_muldiv_c   : std_ulogic_vector(1 downto 0) := "00"; -- multiplication/division operations ('M' extension)
 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
 
  constant cp_sel_atomic_c   : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations; success/failure evaluation ('A' extension)
 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
 
  constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extension)
 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
 
--constant cp_sel_float32_c  : std_ulogic_vector(1 downto 0) := "11"; -- reserved -- single-precision floating point operations ('F' extension)
 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
 
 
 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "100"; -- reserved
 
 
 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "101"; -- reserved
 
 
 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "110"; -- reserved
 
 
 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "111"; -- reserved
 
 
 
 
 
  -- ALU Function Codes ---------------------------------------------------------------------
 
  -- ALU Function Codes ---------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- arithmetic core --
 
  -- arithmetic core --
 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
Line 792... Line 805... 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
Line 834... Line 847... 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
 
 
 
      IO_NCO_EN                    : boolean := true    -- implement numerically-controlled oscillator (NCO)?
 
    );
 
    );
 
    port (
 
    port (
 
      -- Global control --
 
      -- Global control --
 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
 
      -- Wishbone bus interface --
 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
 
      wb_we_o     : out std_ulogic; -- read/write
 
      wb_we_o     : out std_ulogic; -- read/write
Line 855... Line 869... 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
 
      -- GPIO --
 
      -- GPIO (available if IO_GPIO_EN = true) --
 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
 
      -- UART --
 
      -- UART (available if IO_UART_EN = true) --
 
      uart_txd_o  : out std_ulogic; -- UART send data
 
      uart_txd_o  : out std_ulogic; -- UART send data
 
      uart_rxd_i  : in  std_ulogic := '0'; -- UART receive data
 
      uart_rxd_i  : in  std_ulogic := '0'; -- UART receive data
 
      -- SPI --
 
      -- SPI (available if IO_SPI_EN = true) --
 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
 
      -- TWI --
 
      -- TWI (available if IO_TWI_EN = true) --
 
      twi_sda_io  : inout std_logic; -- twi serial data line
 
      twi_sda_io  : inout std_logic; -- twi serial data line
 
      twi_scl_io  : inout std_logic; -- twi serial clock line
 
      twi_scl_io  : inout std_logic; -- twi serial clock line
 
      -- PWM --
 
      -- PWM (available if IO_PWM_EN = true) --
 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
 
      -- Custom Functions Subsystem IO --
 
      -- Custom Functions Subsystem IO --
 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
 
      cfs_out_o   : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
 
      cfs_out_o   : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
 
 
 
      -- NCO output (available if IO_NCO_EN = true) --
 
 
 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
 
      -- Interrupts --
 
      -- Interrupts --
 
      soc_firq_i  : in  std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
 
      soc_firq_i  : in  std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
Line 889... Line 905... 
  -- Component: CPU Top Entity --------------------------------------------------------------
 
  -- Component: CPU Top Entity --------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_cpu
 
  component neorv32_cpu
 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
      -- Extension Options --
 
      -- Extension Options --
 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
 
      -- Physical Memory Protection (PMP) --
 
      -- Physical Memory Protection (PMP) --
 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
Line 958... Line 974... 
  -- Component: CPU Control -----------------------------------------------------------------
 
  -- Component: CPU Control -----------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_cpu_control
 
  component neorv32_cpu_control
 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
      -- Physical memory protection (PMP) --
 
      -- Physical memory protection (PMP) --
 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      -- Hardware Performance Monitors (HPM) --
 
      -- Hardware Performance Monitors (HPM) --
 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
Line 1030... Line 1046... 
      clk_i  : in  std_ulogic; -- global clock, rising edge
 
      clk_i  : in  std_ulogic; -- global clock, rising edge
 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      -- data input --
 
      -- data input --
 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      csr_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
 
 
 
      -- data output --
 
      -- data output --
 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
 
    );
 
    );
Line 1059... Line 1074... 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
      -- data output --
 
      -- data output --
 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
 
      -- co-processor interface --
 
      -- co-processor interface --
 
      cp0_start_o : out std_ulogic; -- trigger co-processor 0
 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
 
      cp0_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
 
      cp0_valid_i : in  std_ulogic; -- co-processor 0 result valid
 
      cp_result_i : in  cp_data_if_t; -- co-processor result
 
      cp1_start_o : out std_ulogic; -- trigger co-processor 1
 
 
 
      cp1_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
 
 
 
      cp1_valid_i : in  std_ulogic; -- co-processor 1 result valid
 
 
 
      cp2_start_o : out std_ulogic; -- trigger co-processor 2
 
 
 
      cp2_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
 
 
 
      cp2_valid_i : in  std_ulogic; -- co-processor 2 result valid
 
 
 
      cp3_start_o : out std_ulogic; -- trigger co-processor 3
 
 
 
      cp3_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
 
 
 
      cp3_valid_i : in  std_ulogic; -- co-processor 3 result valid
 
 
 
      -- status --
 
      -- status --
 
      wait_o      : out std_ulogic -- busy due to iterative processing units
 
      wait_o      : out std_ulogic -- busy due to iterative processing units
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
Line 1551... Line 1557... 
 
 
 
 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_cfs
 
  component neorv32_cfs
 
    generic (
 
    generic (
 
      CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
 
      CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000" -- custom CFS configuration generic
 
    );
 
    );
 
    port (
 
    port (
 
      -- host access --
 
      -- host access --
 
      clk_i       : in  std_ulogic; -- global clock line
 
      clk_i       : in  std_ulogic; -- global clock line
 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
Line 1578... Line 1584... 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
 
      cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
 
      cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  component neorv32_nco
 
 
 
    port (
 
 
 
      -- host access --
 
 
 
      clk_i       : in  std_ulogic; -- global clock line
 
 
 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
 
 
 
      rden_i      : in  std_ulogic; -- read enable
 
 
 
      wren_i      : in  std_ulogic; -- write enable
 
 
 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
 
 
 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
 
 
 
      ack_o       : out std_ulogic; -- transfer acknowledge
 
 
 
      -- clock generator --
 
 
 
      clkgen_en_o : out std_ulogic; -- enable clock generator
 
 
 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
 
 
 
      -- NCO output --
 
 
 
      nco_o       : out std_ulogic_vector(02 downto 0)
 
 
 
    );
 
 
 
  end component;
 
 
 
 
 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_sysinfo
 
  component neorv32_sysinfo
 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
Line 1609... Line 1635... 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
 
      IO_CFS_EN            : boolean := true    -- implement custom functions subsystem (CFS)?
 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
 
 
 
      IO_NCO_EN            : boolean := true    -- implement numerically-controlled oscillator (NCO)?
 
    );
 
    );
 
    port (
 
    port (
 
      -- host access --
 
      -- host access --
 
      clk_i  : in  std_ulogic; -- global clock line
 
      clk_i  : in  std_ulogic; -- global clock line
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address

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