| Line 58... |
Line 58... |
constant pmp_num_regions_critical_c : natural := 8;
|
constant pmp_num_regions_critical_c : natural := 8;
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050204"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050207"; -- no touchy!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
| Line 252... |
Line 252... |
constant ctrl_bus_rd_c : natural := 31; -- read data request
|
constant ctrl_bus_rd_c : natural := 31; -- read data request
|
constant ctrl_bus_wr_c : natural := 32; -- write data request
|
constant ctrl_bus_wr_c : natural := 32; -- write data request
|
constant ctrl_bus_if_c : natural := 33; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 33; -- instruction fetch request
|
constant ctrl_bus_mo_we_c : natural := 34; -- memory address and data output register write enable
|
constant ctrl_bus_mo_we_c : natural := 34; -- memory address and data output register write enable
|
constant ctrl_bus_mi_we_c : natural := 35; -- memory data input register write enable
|
constant ctrl_bus_mi_we_c : natural := 35; -- memory data input register write enable
|
constant ctrl_bus_wd_sel_c : natural := 36; -- memory write-data source select (0=reg_file, 1=co-proc.)
|
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load
|
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions
|
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 40; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation
|
constant ctrl_bus_excl_c : natural := 41; -- exclusive bus access
|
constant ctrl_bus_lock_c : natural := 42; -- locked/exclusive bus access
|
|
-- co-processors --
|
-- co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select ID lsb
|
constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb
|
constant ctrl_cp_id_hsb_c : natural := 44; -- cp select ID hsb
|
constant ctrl_cp_id_hsb_c : natural := 43; -- cp select ID hsb
|
constant ctrl_cp_id_msb_c : natural := 45; -- cp select ID msb
|
constant ctrl_cp_id_msb_c : natural := 44; -- cp select ID msb
|
constant ctrl_cp_fpu_mem_we_c : natural := 46; -- fpu-cp memory-data write enable
|
|
-- current privilege level --
|
-- current privilege level --
|
constant ctrl_priv_lvl_lsb_c : natural := 47; -- privilege level lsb
|
constant ctrl_priv_lvl_lsb_c : natural := 45; -- privilege level lsb
|
constant ctrl_priv_lvl_msb_c : natural := 48; -- privilege level msb
|
constant ctrl_priv_lvl_msb_c : natural := 46; -- privilege level msb
|
-- instruction's control blocks (used by cpu co-processors) --
|
-- instruction's control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct3_0_c : natural := 49; -- funct3 bit 0
|
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
|
constant ctrl_ir_funct3_1_c : natural := 50; -- funct3 bit 1
|
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
|
constant ctrl_ir_funct3_2_c : natural := 51; -- funct3 bit 2
|
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
|
constant ctrl_ir_funct12_0_c : natural := 52; -- funct12 bit 0
|
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
|
constant ctrl_ir_funct12_1_c : natural := 53; -- funct12 bit 1
|
constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1
|
constant ctrl_ir_funct12_2_c : natural := 54; -- funct12 bit 2
|
constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2
|
constant ctrl_ir_funct12_3_c : natural := 55; -- funct12 bit 3
|
constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3
|
constant ctrl_ir_funct12_4_c : natural := 56; -- funct12 bit 4
|
constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4
|
constant ctrl_ir_funct12_5_c : natural := 57; -- funct12 bit 5
|
constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5
|
constant ctrl_ir_funct12_6_c : natural := 58; -- funct12 bit 6
|
constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6
|
constant ctrl_ir_funct12_7_c : natural := 59; -- funct12 bit 7
|
constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7
|
constant ctrl_ir_funct12_8_c : natural := 60; -- funct12 bit 8
|
constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8
|
constant ctrl_ir_funct12_9_c : natural := 61; -- funct12 bit 9
|
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9
|
constant ctrl_ir_funct12_10_c : natural := 62; -- funct12 bit 10
|
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
|
constant ctrl_ir_funct12_11_c : natural := 63; -- funct12 bit 11
|
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
|
constant ctrl_ir_opcode7_0_c : natural := 64; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_1_c : natural := 65; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_2_c : natural := 66; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_3_c : natural := 67; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 68; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 69; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 70; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
-- CPU status --
|
-- CPU status --
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
constant ctrl_sleep_c : natural := 69; -- set when CPU is in sleep mode
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 72; -- control bus size
|
constant ctrl_width_c : natural := 70; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 344... |
Line 342... |
-- system/csr --
|
-- system/csr --
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
-- atomic memory access (A) --
|
-- atomic memory access (A) --
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
-- floating point operations (F/D/H/Q) --
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
constant opcode_flw_c : std_ulogic_vector(6 downto 0) := "0000111"; -- load word
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
|
constant opcode_fsw_c : std_ulogic_vector(6 downto 0) := "0100111"; -- store word
|
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand operation
|
|
constant opcode_fmac_c : std_ulogic_vector(6 downto 0) := "100--11"; -- fused multiply-add (three operands)
|
|
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- control flow --
|
-- control flow --
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
| Line 698... |
Line 693... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
|
constant cp_sel_atomic_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
|
constant cp_sel_atomic_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
|
constant cp_sel_csr_rd_c : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
|
constant cp_sel_csr_rd_c : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('F' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('Zfinx' extension)
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "101"; -- reserved
|
--constant cp_sel_crypto_c : std_ulogic_vector(2 downto 0) := "101"; -- crypto operations ('K' extension)
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 891... |
Line 886... |
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
| Line 958... |
Line 953... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_F : boolean := false; -- implement 32-bit floating-point extension?
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
| Line 984... |
Line 979... |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic := '0'; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1002... |
Line 996... |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
d_bus_excl_o : out std_ulogic; -- exclusive access
|
|
d_bus_excl_i : in std_ulogic; -- state of exclusiv access (set if success)
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
| Line 1027... |
Line 1022... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_F : boolean := false; -- implement 32-bit floating-point extension?
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
| Line 1172... |
Line 1167... |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Co-Processor 32-bit FPU ('F' extension) ---------------------------------
|
-- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_cp_fpu
|
component neorv32_cpu_cp_fpu
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
start_i : in std_ulogic; -- trigger operation
|
start_i : in std_ulogic; -- trigger operation
|
-- data input --
|
-- data input --
|
frm_i : in std_ulogic_vector(2 downto 0); -- rounding mode
|
frm_i : in std_ulogic_vector(2 downto 0); -- rounding mode
|
reg_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read-data
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
-- result and status --
|
-- result and status --
|
fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
|
|
mem_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data
|
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
|
fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Bus Timeout --
|
-- Bus Timeout --
|
| Line 1223... |
Line 1218... |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
--
|
--
|
|
bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
| Line 1241... |
Line 1237... |
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1253... |
Line 1248... |
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_lock_o : out std_ulogic -- locked/exclusive access
|
d_bus_excl_o : out std_ulogic; -- exclusive access request
|
|
d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1278... |
Line 1274... |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_we_i : in std_ulogic; -- write enable
|
host_we_i : in std_ulogic; -- write enable
|
host_re_i : in std_ulogic; -- read enable
|
host_re_i : in std_ulogic; -- read enable
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
host_lock_i : in std_ulogic; -- locked/exclusive access
|
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_err_o : out std_ulogic; -- bus transfer error
|
host_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus interface --
|
-- peripheral bus interface --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic -- bus transfer error
|
bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1314... |
Line 1308... |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
ca_bus_lock_i : in std_ulogic; -- locked/exclusive access
|
ca_bus_excl_i : in std_ulogic; -- exclusive access
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
-- controller interface b --
|
-- controller interface b --
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_lock_i : in std_ulogic; -- locked/exclusive access
|
cb_bus_excl_i : in std_ulogic; -- exclusive access
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
| Line 1337... |
Line 1331... |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
p_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
p_bus_excl_o : out std_ulogic; -- exclusive access
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1611... |
Line 1605... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
lock_i : in std_ulogic; -- locked/exclusive bus access
|
excl_i : in std_ulogic; -- exclusive access request
|
|
excl_o : out std_ulogic; -- state of exclusiv access (set if success)
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
