| Line 43... |
Line 43... |
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- (external) bus interface --
|
-- (external) bus interface --
|
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
|
|
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
|
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
|
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
|
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
|
|
|
-- CPU core --
|
-- CPU core --
|
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
|
constant ipb_entries_c : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
|
|
|
-- "response time window" for processor-internal memories and IO devices
|
|
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural;
|
function index_size_f(input : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
|
function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
|
| Line 79... |
Line 81... |
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050400"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050408"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
|
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
|
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
|
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
|
|
|
-- Internal Types -------------------------------------------------------------------------
|
-- Internal Types -------------------------------------------------------------------------
|
| Line 261... |
Line 263... |
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
|
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions
|
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
|
constant ctrl_bus_excl_c : natural := 41; -- exclusive bus access
|
constant ctrl_bus_lock_c : natural := 41; -- make atomic/exclusive access lock
|
|
constant ctrl_bus_de_lock_c : natural := 42; -- remove atomic/exclusive access
|
|
constant ctrl_bus_ch_lock_c : natural := 43; -- evaluate atomic/exclusive lock (SC operation)
|
-- co-processors --
|
-- co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb
|
constant ctrl_cp_id_lsb_c : natural := 44; -- cp select ID lsb
|
constant ctrl_cp_id_hsb_c : natural := 43; -- cp select ID
|
constant ctrl_cp_id_hsb_c : natural := 45; -- cp select ID
|
constant ctrl_cp_id_msb_c : natural := 44; -- cp select ID msb
|
constant ctrl_cp_id_msb_c : natural := 46; -- cp select ID msb
|
-- current privilege level --
|
|
constant ctrl_priv_lvl_lsb_c : natural := 45; -- privilege level lsb
|
|
constant ctrl_priv_lvl_msb_c : natural := 46; -- privilege level msb
|
|
-- instruction's control blocks (used by cpu co-processors) --
|
-- instruction's control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
|
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
|
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
|
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
|
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
|
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
|
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
|
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
|
| Line 293... |
Line 294... |
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
-- CPU status --
|
-- CPU status --
|
constant ctrl_sleep_c : natural := 69; -- set when CPU is in sleep mode
|
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb
|
|
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb
|
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
|
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 70; -- control bus size
|
constant ctrl_width_c : natural := 73; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 721... |
Line 725... |
-- <<< custom (NEORV32-specific) read-only CSRs >>> --
|
-- <<< custom (NEORV32-specific) read-only CSRs >>> --
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
|
|
-- Co-Processor IDs -----------------------------------------------------------------------
|
-- Co-Processor IDs -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
|
constant cp_sel_csr_rd_c : std_ulogic_vector(2 downto 0) := "000"; -- CSR read access ('Zicsr' extension)
|
constant cp_sel_atomic_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- multiplication/division operations ('M' extension)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
|
constant cp_sel_csr_rd_c : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- floating-point unit ('Zfinx' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('Zfinx' extension)
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "100"; -- reserved
|
--constant cp_sel_crypto_c : std_ulogic_vector(2 downto 0) := "101"; -- crypto operations ('K' extension)
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "101"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
|
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 871... |
Line 875... |
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
| Line 899... |
Line 903... |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
|
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
| Line 921... |
Line 926... |
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
| Line 982... |
Line 987... |
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
| Line 1017... |
Line 1021... |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic := '0'; -- cancel current bus transaction
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
-- data bus interface --
|
-- data bus interface --
|
| Line 1029... |
Line 1033... |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_excl_o : out std_ulogic; -- exclusive access
|
|
d_bus_excl_i : in std_ulogic; -- state of exclusiv access (set if success)
|
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
| Line 1083... |
Line 1085... |
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- status input --
|
-- status input --
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
bus_i_wait_i : in std_ulogic; -- wait for bus
|
bus_i_wait_i : in std_ulogic; -- wait for bus
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
|
excl_state_i : in std_ulogic; -- atomic/exclusive access lock status
|
-- data input --
|
-- data input --
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
| Line 1238... |
Line 1241... |
generic (
|
generic (
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024 -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Bus Timeout --
|
|
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 1261... |
Line 1262... |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
--
|
--
|
bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
|
excl_state_o : out std_ulogic; -- atomic/exclusive access status
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
| Line 1276... |
Line 1277... |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_fence_o : out std_ulogic -- fence operation
|
d_bus_excl_o : out std_ulogic; -- exclusive access request
|
);
|
d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
|
end component;
|
|
|
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_bus_keeper is
|
|
generic (
|
|
-- Internal instruction memory --
|
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
|
-- Internal data memory --
|
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes
|
|
);
|
|
port (
|
|
-- host access --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
rden_i : in std_ulogic; -- read enable
|
|
wren_i : in std_ulogic; -- write enable
|
|
ack_i : in std_ulogic; -- transfer acknowledge from bus system
|
|
err_i : in std_ulogic; -- transfer error from bus system
|
|
err_o : out std_ulogic -- bus error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1316... |
Line 1339... |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_we_i : in std_ulogic; -- write enable
|
host_we_i : in std_ulogic; -- write enable
|
host_re_i : in std_ulogic; -- read enable
|
host_re_i : in std_ulogic; -- read enable
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_err_o : out std_ulogic; -- bus transfer error
|
host_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus interface --
|
-- peripheral bus interface --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic -- bus transfer error
|
bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1350... |
Line 1371... |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_we_i : in std_ulogic; -- write enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_re_i : in std_ulogic; -- read enable
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
ca_bus_lock_i : in std_ulogic; -- exclusive access request
|
ca_bus_excl_i : in std_ulogic; -- exclusive access
|
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
-- controller interface b --
|
-- controller interface b --
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_we_i : in std_ulogic; -- write enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_lock_i : in std_ulogic; -- exclusive access request
|
cb_bus_excl_i : in std_ulogic; -- exclusive access
|
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_re_o : out std_ulogic; -- read enable
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
p_bus_lock_o : out std_ulogic; -- exclusive access request
|
p_bus_excl_o : out std_ulogic; -- exclusive access
|
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1633... |
Line 1651... |
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Bus Timeout --
|
|
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
| Line 1647... |
Line 1667... |
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
lock_i : in std_ulogic; -- exclusive access request
|
excl_i : in std_ulogic; -- exclusive access request
|
|
excl_o : out std_ulogic; -- state of exclusiv access (set if success)
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
