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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Diff between revs 60 and 61

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Rev 60 Rev 61
Line 43... Line 43... 
  -- address space --
 
  -- address space --
 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
 
 
 
 
 
  -- external bus interface --
 
  -- external bus interface --
 
  constant wb_pipe_mode_c    : boolean := false; -- external bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
 
  constant wb_pipe_mode_c  : boolean := false; -- protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
 
  constant xbus_big_endian_c : boolean := false; -- external memory access byte order: true=big-endian, false=little-endian (default)
 
  constant wb_big_endian_c : boolean := false; -- byte order: true=big-endian, false=little-endian (default)
 
 
 
  constant wb_rx_buffer_c  : boolean := true;  -- use register buffer for RX data when true (default)
 
 
 
 
 
  -- CPU core --
 
  -- CPU core --
 
  constant ipb_entries_c     : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
 
  constant ipb_entries_c     : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
 
  constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
 
  constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
 
  constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
 
  constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
Line 64... Line 65... 
  -- jtag tap - identifier --
 
  -- jtag tap - identifier --
 
  constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
 
  constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
 
  constant jtag_tap_idcode_partid_c  : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
 
  constant jtag_tap_idcode_partid_c  : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
 
  constant jtag_tap_idcode_manid_c   : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
 
  constant jtag_tap_idcode_manid_c   : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
 
 
 
 
 
 
 
  -- Architecture Constants (do not modify!) ------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
 
 
 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050710"; -- no touchy!
 
 
 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
 
 
 
  constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
 
 
 
 
 
 
 
  -- External Interface Types ---------------------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  type sdata_8x32_t  is array (0 to 7)  of std_ulogic_vector(31 downto 0);
 
 
 
  type sdata_8x32r_t is array (0 to 7)  of std_logic_vector(31 downto 0); -- resolved type
 
 
 
 
 
 
 
  -- Internal Interface Types ---------------------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
 
 
 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
 
 
 
  type cp_data_if_t  is array (0 to 3)  of std_ulogic_vector(data_width_c-1 downto 0);
 
 
 
 
 
 
 
  -- Internal Memory Types Configuration Types ----------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries
 
 
 
  type mem8_t  is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries
 
 
 
 
 
  -- Helper Functions -----------------------------------------------------------------------
 
  -- Helper Functions -----------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  function index_size_f(input : natural) return natural;
 
  function index_size_f(input : natural) return natural;
 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
Line 81... Line 105... 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
 
  function is_power_of_two_f(input : natural) return boolean;
 
  function is_power_of_two_f(input : natural) return boolean;
 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
 
 
 
  function char_tolower_f(ch : character) return character;
 
 
 
  function str_equal_f(str0 : string; str1 : string) return boolean;
 
 
 
  impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
 
 
 
 
 
  -- Architecture Constants (do not modify!) ------------------------------------------------
 
  -- Internal (auto-generated) Configurations -----------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
 
 
 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050605"; -- no touchy!
 
 
 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
 
 
 
  constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
 
 
 
  constant def_rst_val_c  : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
 
  constant def_rst_val_c  : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
 
 
 
 
 
  -- Internal Types -------------------------------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
 
 
 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
 
 
 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
 
 
 
 
 
 
 
  -- Processor-Internal Address Space Layout ------------------------------------------------
 
  -- Processor-Internal Address Space Layout ------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
 
  --> internal data/instruction memory sizes are configured via top's generics
 
  --> internal data/instruction memory sizes are configured via top's generics
 
 
 
 
 
  -- Internal Bootloader ROM --
 
  -- Internal Bootloader ROM --
 
 
 
  -- Actual bootloader size is determined during runtime via the length of the bootloader initialization image
 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space size in bytes, fixed!
 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
 
 
 
 
 
 
 
  -- On-Chip Debugger: Debug Module --
 
  -- On-Chip Debugger: Debug Module --
 
  constant dm_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; -- base address, fixed!
 
  constant dm_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; -- base address, fixed!
 
  constant dm_size_c            : natural := 4*32*4; -- debug ROM address space in bytes, fixed
 
  constant dm_size_c            : natural := 4*32*4; -- debug ROM address space size in bytes, fixed
 
  constant dm_code_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800";
 
  constant dm_code_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800";
 
  constant dm_pbuf_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";
 
  constant dm_pbuf_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";
 
  constant dm_data_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";
 
  constant dm_data_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";
 
  constant dm_sreg_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";
 
  constant dm_sreg_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";
 
 
 
 
 
  -- IO: Peripheral Devices ("IO") Area --
 
  -- IO: Peripheral Devices ("IO") Area --
 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
 
  constant io_size_c            : natural := 512; -- module's address space in bytes, fixed!
 
  constant io_size_c            : natural := 512; -- IO address space size in bytes, fixed!
 
 
 
 
 
  -- Custom Functions Subsystem (CFS) --
 
  -- Custom Functions Subsystem (CFS) --
 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address
 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address
 
  constant cfs_size_c           : natural := 64*4; -- module's address space in bytes
 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe04";
 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe04";
 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe08";
 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe08";
 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe0c";
 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe0c";
 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe10";
 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe10";
Line 159... Line 176... 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe78";
 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe78";
 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe7c";
 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe7c";
 
 
 
 
 
  -- Pulse-Width Modulation Controller (PWM) --
 
  -- Pulse-Width Modulation Controller (PWM) --
 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80"; -- base address
 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80"; -- base address
 
  constant pwm_size_c           : natural := 16*4; -- module's address space in bytes
 
  constant pwm_size_c           : natural := 16*4; -- module's address space size in bytes
 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80";
 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80";
 
  constant pwm_duty0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe84";
 
  constant pwm_duty0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe84";
 
  constant pwm_duty1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe88";
 
  constant pwm_duty1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe88";
 
  constant pwm_duty2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe8c";
 
  constant pwm_duty2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe8c";
 
  constant pwm_duty3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe90";
 
  constant pwm_duty3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe90";
Line 177... Line 194... 
  constant pwm_duty11_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb0";
 
  constant pwm_duty11_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb0";
 
  constant pwm_duty12_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb4";
 
  constant pwm_duty12_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb4";
 
  constant pwm_duty13_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb8";
 
  constant pwm_duty13_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb8";
 
  constant pwm_duty14_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffebc";
 
  constant pwm_duty14_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffebc";
 
 
 
 
 
  -- reserved --
 
  -- Stream link interface (SLINK) --
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
 
  constant slink_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec0"; -- base address
 
--constant reserved_size_c      : natural := 16*4; -- module's address space in bytes
 
  constant slink_size_c         : natural := 16*4; -- module's address space size in bytes
 
 
 
 
 
  -- reserved --
 
  -- reserved --
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
 
--constant reserved_size_c      : natural := 32*4; -- module's address space in bytes
 
--constant reserved_size_c      : natural := 32*4; -- module's address space size in bytes
 
 
 
 
 
  -- General Purpose Input/Output Unit (GPIO) --
 
  -- External Interrupt Controller (XIRQ) --
 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
 
  constant xirq_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
 
  constant xirq_size_c          : natural := 4*4; -- module's address space size in bytes
 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
 
  constant xirq_enable_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
 
  constant xirq_pending_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
 
 
 
  constant xirq_source_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
 
  -- True Random Number Generator (TRNG) --
 
--constant xirq_res_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88"; -- base address
 
 
 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
 
 
 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
 
 
 
 
 
 
 
  -- Watch Dog Timer (WDT) --
 
 
 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c"; -- base address
 
 
 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
 
 
 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
 
 
 
 
 
 
 
  -- Machine System Timer (MTIME) --
 
  -- Machine System Timer (MTIME) --
 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
 
  constant mtime_size_c         : natural := 4*4; -- module's address space size in bytes
 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
 
 
 
 
 
  -- Primary Universal Asynchronous Receiver/Transmitter (UART0) --
 
  -- Primary Universal Asynchronous Receiver/Transmitter (UART0) --
 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
 
  constant uart0_size_c         : natural := 2*4; -- module's address space size in bytes
 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
 
 
 
 
 
  -- Serial Peripheral Interface (SPI) --
 
  -- Serial Peripheral Interface (SPI) --
 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address
 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address
 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
 
  constant spi_size_c           : natural := 2*4; -- module's address space size in bytes
 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8";
 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8";
 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac";
 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac";
 
 
 
 
 
  -- Two Wire Interface (TWI) --
 
  -- Two Wire Interface (TWI) --
 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address
 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address
 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
 
  constant twi_size_c           : natural := 2*4; -- module's address space size in bytes
 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";
 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";
 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";
 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";
 
 
 
 
 
  -- reserved --
 
  -- True Random Number Generator (TRNG) --
 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
 
--constant reserved_size_c      : natural := 2*4; -- module's address space in bytes
 
  constant trng_size_c          : natural := 1*4; -- module's address space size in bytes
 
 
 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8";
 
 
 
 
 
 
 
  -- Watch Dog Timer (WDT) --
 
 
 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc"; -- base address
 
 
 
  constant wdt_size_c           : natural := 1*4; -- module's address space size in bytes
 
 
 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc";
 
 
 
 
 
  -- Numerically-Controlled Oscillator (NCO) --
 
  -- reserved --
 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
 
  constant gpio_size_c          : natural := 4*4; -- module's address space size in bytes
 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
 
  constant gpio_in_lo_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
 
  constant gpio_in_hi_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
 
  constant gpio_out_lo_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
 
  constant gpio_out_hi_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
 
 
 
 
 
  -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
 
  -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
 
  constant uart1_size_c         : natural := 2*4; -- module's address space size in bytes
 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
 
 
 
 
 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address
 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address
 
  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes
 
  constant neoled_size_c        : natural := 2*4; -- module's address space size in bytes
 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8";
 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8";
 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc";
 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc";
 
 
 
 
 
  -- System Information Memory (SYSINFO) --
 
  -- System Information Memory (SYSINFO) --
 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space size in bytes
 
 
 
 
 
  -- Main CPU Control Bus -------------------------------------------------------------------
 
  -- Main CPU Control Bus -------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- register file --
 
  -- register file --
 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
Line 288... Line 303... 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
 
 
 
  constant ctrl_alu_frm0_c      : natural := 29; -- FPU rounding mode bit 0
 
 
 
  constant ctrl_alu_frm1_c      : natural := 30; -- FPU rounding mode bit 1
 
 
 
  constant ctrl_alu_frm2_c      : natural := 31; -- FPU rounding mode bit 2
 
  -- bus interface --
 
  -- bus interface --
 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
 
  constant ctrl_bus_size_lsb_c  : natural := 32; -- transfer size lsb (00=byte, 01=half-word)
 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
 
  constant ctrl_bus_size_msb_c  : natural := 33; -- transfer size msb (10=word, 11=?)
 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
 
  constant ctrl_bus_rd_c        : natural := 34; -- read data request
 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
 
  constant ctrl_bus_wr_c        : natural := 35; -- write data request
 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
 
  constant ctrl_bus_if_c        : natural := 36; -- instruction fetch request
 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
 
  constant ctrl_bus_mo_we_c     : natural := 37; -- memory address and data output register write enable
 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
 
  constant ctrl_bus_mi_we_c     : natural := 38; -- memory data input register write enable
 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
 
  constant ctrl_bus_unsigned_c  : natural := 39; -- is unsigned load
 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
 
  constant ctrl_bus_ierr_ack_c  : natural := 40; -- acknowledge instruction fetch bus exceptions
 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
 
  constant ctrl_bus_derr_ack_c  : natural := 41; -- acknowledge data access bus exceptions
 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
 
  constant ctrl_bus_fence_c     : natural := 42; -- executed fence operation
 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
 
  constant ctrl_bus_fencei_c    : natural := 43; -- executed fencei operation
 
  constant ctrl_bus_lock_c      : natural := 41; -- make atomic/exclusive access lock
 
  constant ctrl_bus_lock_c      : natural := 44; -- make atomic/exclusive access lock
 
  constant ctrl_bus_de_lock_c   : natural := 42; -- remove atomic/exclusive access 
  constant ctrl_bus_de_lock_c   : natural := 45; -- remove atomic/exclusive access 
  constant ctrl_bus_ch_lock_c   : natural := 43; -- evaluate atomic/exclusive lock (SC operation)
 
  constant ctrl_bus_ch_lock_c   : natural := 46; -- evaluate atomic/exclusive lock (SC operation)
 
  -- co-processors --
 
  -- co-processors --
 
  constant ctrl_cp_id_lsb_c     : natural := 44; -- cp select ID lsb
 
  constant ctrl_cp_id_lsb_c     : natural := 47; -- cp select ID lsb
 
  constant ctrl_cp_id_hsb_c     : natural := 45; -- cp select ID
 
  constant ctrl_cp_id_msb_c     : natural := 48; -- cp select ID msb
 
  constant ctrl_cp_id_msb_c     : natural := 46; -- cp select ID msb
 
 
 
  -- instruction's control blocks (used by cpu co-processors) --
 
  -- instruction's control blocks (used by cpu co-processors) --
 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
 
  constant ctrl_ir_funct3_0_c   : natural := 49; -- funct3 bit 0
 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
 
  constant ctrl_ir_funct3_1_c   : natural := 50; -- funct3 bit 1
 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
 
  constant ctrl_ir_funct3_2_c   : natural := 51; -- funct3 bit 2
 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
 
  constant ctrl_ir_funct12_0_c  : natural := 52; -- funct12 bit 0
 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
 
  constant ctrl_ir_funct12_1_c  : natural := 53; -- funct12 bit 1
 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
 
  constant ctrl_ir_funct12_2_c  : natural := 54; -- funct12 bit 2
 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
 
  constant ctrl_ir_funct12_3_c  : natural := 55; -- funct12 bit 3
 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
 
  constant ctrl_ir_funct12_4_c  : natural := 56; -- funct12 bit 4
 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
 
  constant ctrl_ir_funct12_5_c  : natural := 57; -- funct12 bit 5
 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
 
  constant ctrl_ir_funct12_6_c  : natural := 58; -- funct12 bit 6
 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
 
  constant ctrl_ir_funct12_7_c  : natural := 59; -- funct12 bit 7
 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
 
  constant ctrl_ir_funct12_8_c  : natural := 60; -- funct12 bit 8
 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
 
  constant ctrl_ir_funct12_9_c  : natural := 61; -- funct12 bit 9
 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
 
  constant ctrl_ir_funct12_10_c : natural := 62; -- funct12 bit 10
 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
 
  constant ctrl_ir_funct12_11_c : natural := 63; -- funct12 bit 11
 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
 
  constant ctrl_ir_opcode7_0_c  : natural := 64; -- opcode7 bit 0
 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
 
  constant ctrl_ir_opcode7_1_c  : natural := 65; -- opcode7 bit 1
 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
 
  constant ctrl_ir_opcode7_2_c  : natural := 66; -- opcode7 bit 2
 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
 
  constant ctrl_ir_opcode7_3_c  : natural := 67; -- opcode7 bit 3
 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
 
  constant ctrl_ir_opcode7_4_c  : natural := 68; -- opcode7 bit 4
 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
 
  constant ctrl_ir_opcode7_5_c  : natural := 69; -- opcode7 bit 5
 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
 
  constant ctrl_ir_opcode7_6_c  : natural := 70; -- opcode7 bit 6
 
  -- CPU status --
 
  -- CPU status --
 
  constant ctrl_priv_lvl_lsb_c  : natural := 69; -- privilege level lsb
 
  constant ctrl_priv_lvl_lsb_c  : natural := 71; -- privilege level lsb
 
  constant ctrl_priv_lvl_msb_c  : natural := 70; -- privilege level msb
 
  constant ctrl_priv_lvl_msb_c  : natural := 72; -- privilege level msb
 
  constant ctrl_sleep_c         : natural := 71; -- set when CPU is in sleep mode
 
  constant ctrl_sleep_c         : natural := 73; -- set when CPU is in sleep mode
 
  constant ctrl_trap_c          : natural := 72; -- set when CPU is entering trap execution
 
  constant ctrl_trap_c          : natural := 74; -- set when CPU is entering trap execution
 
  constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set
 
  constant ctrl_debug_running_c : natural := 75; -- CPU is in debug mode when set
 
  -- control bus size --
 
  -- control bus size --
 
  constant ctrl_width_c         : natural := 74; -- control bus size
 
  constant ctrl_width_c         : natural := 76; -- control bus size
 
 
 
 
 
  -- Comparator Bus -------------------------------------------------------------------------
 
  -- Comparator Bus -------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  constant cmp_equal_c : natural := 0;
 
  constant cmp_equal_c : natural := 0;
 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
Line 696... Line 713... 
  -- user counters/timers --
 
  -- user counters/timers --
 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
 
  --
 
  --
 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
 
 
 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
 
 
 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
 
 
 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
 
 
 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
 
 
 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
 
 
 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
 
 
 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
 
 
 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
 
 
 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
 
 
 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
 
 
 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
 
 
 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
 
 
 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
 
 
 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
 
 
 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
 
 
 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
 
 
 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
 
 
 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
 
 
 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
 
 
 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
 
 
 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
 
 
 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
 
 
 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
 
 
 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
 
 
 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
 
 
 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
 
 
 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
 
 
 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
 
 
 
  --
 
 
 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
 
  --
 
 
 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
 
 
 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
 
 
 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
 
 
 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
 
 
 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
 
 
 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
 
 
 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
 
 
 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
 
 
 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
 
 
 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
 
 
 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
 
 
 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
 
 
 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
 
 
 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
 
 
 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
 
 
 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
 
 
 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
 
 
 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
 
 
 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
 
 
 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
 
 
 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
 
 
 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
 
 
 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
 
 
 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
 
 
 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
 
 
 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
 
 
 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
 
 
 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
 
 
 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
 
 
 
  -- machine information registers --
 
  -- machine information registers --
 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
 
  -- <<< custom (NEORV32-specific) read-only CSRs >>> --
 
  -- <<< custom (NEORV32-specific) read-only CSRs >>> --
 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
 
 
 
 
 
  -- Co-Processor IDs -----------------------------------------------------------------------
 
  -- Co-Processor IDs -----------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "000"; -- CSR read access ('Zicsr' extension)
 
  constant cp_sel_shifter_c  : std_ulogic_vector(1 downto 0) := "00"; -- shift operation
 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "001"; -- multiplication/division operations ('M' extension)
 
  constant cp_sel_muldiv_c   : std_ulogic_vector(1 downto 0) := "01"; -- multiplication/division operations ('M' extension)
 
--constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
 
--constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extension)
 
  constant cp_sel_fpu_c      : std_ulogic_vector(2 downto 0) := "011"; -- floating-point unit ('Zfinx' extension)
 
  constant cp_sel_fpu_c      : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension)
 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "100"; -- reserved
 
 
 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "101"; -- reserved
 
 
 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
 
 
 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
 
 
 
 
 
 
 
  -- ALU Function Codes ---------------------------------------------------------------------
 
  -- ALU Function Codes ---------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- arithmetic core --
 
  -- arithmetic core --
 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
Line 791... Line 744... 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
 
  -- function select (actual alu result) --
 
  -- function select (actual alu result) --
 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (multi-cycle)
 
  constant alu_func_cmd_csrr_c    : std_ulogic_vector(1 downto 0) := "10"; -- r <= CSR read
 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
 
 
 
 
 
  -- Trap ID Codes --------------------------------------------------------------------------
 
  -- Trap ID Codes --------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- MSB   : 1 = async exception (IRQ); 0 = sync exception (e.g. ebreak)
 
  -- MSB   : 1 = async exception (IRQ); 0 = sync exception (e.g. ebreak)
Line 922... Line 875... 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_top
 
  component neorv32_top
 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
 
 
 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
 
 
 
      INT_BOOTLOADER_EN            : boolean := true;   -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
 
      -- On-Chip Debugger (OCD) --
 
      -- On-Chip Debugger (OCD) --
 
      ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
 
      ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement mul/div extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
 
 
 
      CPU_EXTENSION_RISCV_Zmmul    : boolean := false; -- implement multiply-only M sub-extension?
 
      -- Extension Options --
 
      -- Extension Options --
 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
 
      TINY_SHIFT_EN                : boolean := false;  -- use tiny (single-bit) shifter for shift operations
 
 
 
      CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
 
      CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
 
      -- Physical Memory Protection (PMP) --
 
      -- Physical Memory Protection (PMP) --
 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      -- Hardware Performance Monitors (HPM) --
 
      -- Hardware Performance Monitors (HPM) --
 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
 
      HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (0..64)
 
      HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (0..64)
 
      -- Internal Instruction memory --
 
      -- Internal Instruction memory (IMEM) --
 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
 
      -- Internal Data memory (DMEM) --
 
      -- Internal Data memory --
 
 
 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
 
      -- Internal Cache memory --
 
      -- Internal Cache memory (iCACHE) --
 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
 
      -- External memory interface --
 
      -- External memory interface (WISHBONE) --
 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
 
      MEM_EXT_TIMEOUT              : natural := 255;    -- cycles after a pending bus access auto-terminates (0 = disabled)
 
      MEM_EXT_TIMEOUT              : natural := 255;    -- cycles after a pending bus access auto-terminates (0 = disabled)
 
 
 
      -- Stream link interface (SLINK) --
 
 
 
      SLINK_NUM_TX                 : natural := 0;      -- number of TX links (0..8)
 
 
 
      SLINK_NUM_RX                 : natural := 0;      -- number of TX links (0..8)
 
 
 
      SLINK_TX_FIFO                : natural := 1;      -- TX fifo depth, has to be a power of two
 
 
 
      SLINK_RX_FIFO                : natural := 1;      -- RX fifo depth, has to be a power of two
 
 
 
      -- External Interrupts Controller (XIRQ) --
 
 
 
      XIRQ_NUM_CH                  : natural := 0;      -- number of external IRQ channels (0..32)
 
 
 
      XIRQ_TRIGGER_TYPE            : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
 
 
 
      XIRQ_TRIGGER_POLARITY        : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
 
      -- Processor peripherals --
 
      -- Processor peripherals --
 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
Line 976... Line 937... 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
 
      IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
 
 
 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
 
    );
 
    );
 
    port (
 
    port (
 
      -- Global control --
 
      -- Global control --
 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
Line 1004... Line 964... 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
 
 
 
      -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
 
 
 
      slink_tx_dat_o : out sdata_8x32_t; -- output data
 
 
 
      slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
 
 
 
      slink_tx_rdy_i : in  std_ulogic_vector(7 downto 0) := (others => '0'); -- ready to send
 
 
 
      -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
 
 
 
      slink_rx_dat_i : in  sdata_8x32_t := (others => (others => '0')); -- input data
 
 
 
      slink_rx_val_i : in  std_ulogic_vector(7 downto 0) := (others => '0'); -- valid input
 
 
 
      slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
 
      -- GPIO (available if IO_GPIO_EN = true) --
 
      -- GPIO (available if IO_GPIO_EN = true) --
 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
 
      gpio_o         : out std_ulogic_vector(63 downto 0); -- parallel output
 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
 
      gpio_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- parallel input
 
      -- primary UART0 (available if IO_UART0_EN = true) --
 
      -- primary UART0 (available if IO_UART0_EN = true) --
 
      uart0_txd_o : out std_ulogic; -- UART0 send data
 
      uart0_txd_o : out std_ulogic; -- UART0 send data
 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
Line 1030... Line 998... 
      -- PWM (available if IO_PWM_NUM_CH > 0) --
 
      -- PWM (available if IO_PWM_NUM_CH > 0) --
 
      pwm_o       : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
 
      pwm_o       : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
 
      -- Custom Functions Subsystem IO --
 
      -- Custom Functions Subsystem IO --
 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
 
      -- NCO output (available if IO_NCO_EN = true) --
 
 
 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
 
 
 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
 
      neoled_o    : out std_ulogic; -- async serial data line
 
      neoled_o    : out std_ulogic; -- async serial data line
 
      -- System time --
 
      -- System time --
 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
 
      mtime_o     : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
 
      mtime_o     : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
 
      -- Interrupts --
 
      -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
 
 
 
      xirq_i         : in  std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
 
 
 
      -- CPU Interrupts --
 
      nm_irq_i    : in  std_ulogic := '0'; -- non-maskable interrupt
 
      nm_irq_i    : in  std_ulogic := '0'; -- non-maskable interrupt
 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
 
 
 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
 
    );
 
    );
 
  end component;
 
  end component;
Line 1058... Line 1025... 
      CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
 
      CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement mul/div extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
 
 
      CPU_EXTENSION_RISCV_Zmmul    : boolean := false; -- implement multiply-only M sub-extension?
 
      CPU_EXTENSION_RISCV_DEBUG    : boolean := false; -- implement CPU debug mode?
 
      CPU_EXTENSION_RISCV_DEBUG    : boolean := false; -- implement CPU debug mode?
 
      -- Extension Options --
 
      -- Extension Options --
 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
 
      TINY_SHIFT_EN                : boolean := false; -- use tiny (single-bit) shifter for shift operations
 
 
 
      CPU_CNT_WIDTH                : natural := 64;    -- total width of CPU cycle and instret counters (0..64)
 
      CPU_CNT_WIDTH                : natural := 64;    -- total width of CPU cycle and instret counters (0..64)
 
      -- Physical Memory Protection (PMP) --
 
      -- Physical Memory Protection (PMP) --
 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
 
      -- Hardware Performance Monitors (HPM) --
 
      -- Hardware Performance Monitors (HPM) --
Line 1115... Line 1082... 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
 
      -- fast interrupts (custom) --
 
      -- fast interrupts (custom) --
 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
 
      firq_ack_o     : out std_ulogic_vector(15 downto 0);
 
 
 
      -- debug mode (halt) request --
 
      -- debug mode (halt) request --
 
      db_halt_req_i  : in  std_ulogic := '0'
 
      db_halt_req_i  : in  std_ulogic := '0'
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
Line 1133... Line 1099... 
      CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
 
      CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
 
      -- RISC-V CPU Extensions --
 
      -- RISC-V CPU Extensions --
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement mul/div extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
 
 
      CPU_EXTENSION_RISCV_Zmmul    : boolean := false; -- implement multiply-only M sub-extension?
 
      CPU_EXTENSION_RISCV_DEBUG    : boolean := false; -- implement CPU debug mode?
 
      CPU_EXTENSION_RISCV_DEBUG    : boolean := false; -- implement CPU debug mode?
 
      -- Extension Options --
 
      -- Extension Options --
 
      CPU_CNT_WIDTH                : natural := 64; -- total width of CPU cycle and instret counters (0..64)
 
      CPU_CNT_WIDTH                : natural := 64; -- total width of CPU cycle and instret counters (0..64)
 
      -- Physical memory protection (PMP) --
 
      -- Physical memory protection (PMP) --
 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
Line 1154... Line 1121... 
      -- global control --
 
      -- global control --
 
      clk_i         : in  std_ulogic; -- global clock, rising edge
 
      clk_i         : in  std_ulogic; -- global clock, rising edge
 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      -- status input --
 
      -- status input --
 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
 
      alu_idone_i   : in  std_ulogic; -- ALU iterative operation done
 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
 
      excl_state_i  : in  std_ulogic; -- atomic/exclusive access lock status
 
      excl_state_i  : in  std_ulogic; -- atomic/exclusive access lock status
 
      -- data input --
 
      -- data input --
 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
Line 1169... Line 1136... 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
 
      -- FPU interface --
 
      -- FPU interface --
 
      fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
 
 
 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
 
      -- debug mode (halt) request --
 
      -- debug mode (halt) request --
 
      db_halt_req_i : in  std_ulogic;
 
      db_halt_req_i : in  std_ulogic;
 
      -- non-maskable interrupt --
 
      -- non-maskable interrupt --
 
      nm_irq_i      : in  std_ulogic;
 
      nm_irq_i      : in  std_ulogic;
Line 1181... Line 1147... 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
 
      -- fast interrupts (custom) --
 
      -- fast interrupts (custom) --
 
      firq_i        : in  std_ulogic_vector(15 downto 0);
 
      firq_i        : in  std_ulogic_vector(15 downto 0);
 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
 
 
 
      -- system time input from MTIME --
 
      -- system time input from MTIME --
 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
 
      -- physical memory protection --
 
      -- physical memory protection --
 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
Line 1222... Line 1187... 
 
 
 
 
  -- Component: CPU ALU ---------------------------------------------------------------------
 
  -- Component: CPU ALU ---------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_cpu_alu
 
  component neorv32_cpu_alu
 
    generic (
 
    generic (
 
      CPU_EXTENSION_RISCV_M : boolean := true;  -- implement muld/div extension?
 
      -- RISC-V CPU Extensions --
 
      FAST_SHIFT_EN         : boolean := false; -- use barrel shifter for shift operations
 
      CPU_EXTENSION_RISCV_M     : boolean := false; -- implement mul/div extension?
 
      TINY_SHIFT_EN         : boolean := false  -- use tiny (single-bit) shifter for shift operations
 
      CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
 
 
 
      CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
 
 
 
      -- Extension Options --
 
 
 
      FAST_MUL_EN               : boolean := false; -- use DSPs for M extension's multiplier
 
 
 
      FAST_SHIFT_EN             : boolean := false  -- use barrel shifter for shift operations
 
    );
 
    );
 
    port (
 
    port (
 
      -- global control --
 
      -- global control --
 
      clk_i       : in  std_ulogic; -- global clock, rising edge
 
      clk_i       : in  std_ulogic; -- global clock, rising edge
 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
Line 1236... Line 1205... 
      -- data input --
 
      -- data input --
 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
 
 
      csr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
 
 
 
      cmp_i       : in  std_ulogic_vector(1 downto 0); -- comparator status
 
      -- data output --
 
      -- data output --
 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
 
      -- co-processor interface --
 
      fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
 
 
 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
 
 
 
      cp_result_i : in  cp_data_if_t; -- co-processor result
 
 
 
      -- status --
 
      -- status --
 
      wait_o      : out std_ulogic -- busy due to iterative processing units
 
      idone_o     : out std_ulogic -- iterative processing units done?
 
 
 
    );
 
 
 
  end component;
 
 
 
 
 
 
 
  -- Component: CPU Co-Processor SHIFTER ----------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  component neorv32_cpu_cp_shifter
 
 
 
    generic (
 
 
 
      FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
 
 
 
    );
 
 
 
    port (
 
 
 
      -- global control --
 
 
 
      clk_i   : in  std_ulogic; -- global clock, rising edge
 
 
 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
 
 
 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
 
 
      start_i : in  std_ulogic; -- trigger operation
 
 
 
      -- data input --
 
 
 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
 
 
 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
 
 
 
      imm_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
 
 
 
      -- result and status --
 
 
 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
 
 
 
      valid_o : out std_ulogic -- data output valid
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_cpu_cp_muldiv
 
  component neorv32_cpu_cp_muldiv
 
    generic (
 
    generic (
 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
 
      FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
 
 
 
      DIVISION_EN : boolean := true   -- implement divider hardware
 
    );
 
    );
 
    port (
 
    port (
 
      -- global control --
 
      -- global control --
 
      clk_i   : in  std_ulogic; -- global clock, rising edge
 
      clk_i   : in  std_ulogic; -- global clock, rising edge
 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
Line 1279... Line 1270... 
      clk_i    : in  std_ulogic; -- global clock, rising edge
 
      clk_i    : in  std_ulogic; -- global clock, rising edge
 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
 
      start_i  : in  std_ulogic; -- trigger operation
 
      start_i  : in  std_ulogic; -- trigger operation
 
      -- data input --
 
      -- data input --
 
      frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode
 
 
 
      cmp_i    : in  std_ulogic_vector(1 downto 0); -- comparator status
 
      cmp_i    : in  std_ulogic_vector(1 downto 0); -- comparator status
 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
 
      -- result and status --
 
      -- result and status --
 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
Line 1475... Line 1465... 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_imem
 
  component neorv32_imem
 
    generic (
 
    generic (
 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
 
      IMEM_AS_IROM : boolean := false   -- implement IMEM as pre-initialized read-only memory?
 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
 
 
 
    );
 
    );
 
    port (
 
    port (
 
      clk_i  : in  std_ulogic; -- global clock line
 
      clk_i  : in  std_ulogic; -- global clock line
 
      rden_i : in  std_ulogic; -- read enable
 
      rden_i : in  std_ulogic; -- read enable
 
      wren_i : in  std_ulogic; -- write enable
 
      wren_i : in  std_ulogic; -- write enable
Line 1513... Line 1502... 
 
 
 
 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_boot_rom
 
  component neorv32_boot_rom
 
    generic (
 
    generic (
 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000" -- boot ROM base address
 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
 
 
 
    );
 
    );
 
    port (
 
    port (
 
      clk_i  : in  std_ulogic; -- global clock line
 
      clk_i  : in  std_ulogic; -- global clock line
 
      rden_i : in  std_ulogic; -- read enable
 
      rden_i : in  std_ulogic; -- read enable
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
Line 1557... Line 1545... 
      wren_i : in  std_ulogic; -- write enable
 
      wren_i : in  std_ulogic; -- write enable
 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
 
      ack_o  : out std_ulogic; -- transfer acknowledge
 
      ack_o  : out std_ulogic; -- transfer acknowledge
 
      -- parallel io --
 
      -- parallel io --
 
      gpio_o : out std_ulogic_vector(31 downto 0);
 
      gpio_o : out std_ulogic_vector(63 downto 0);
 
      gpio_i : in  std_ulogic_vector(31 downto 0);
 
      gpio_i : in  std_ulogic_vector(63 downto 0)
 
      -- interrupt --
 
 
 
      irq_o  : out std_ulogic
 
 
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
Line 1706... Line 1692... 
 
 
 
 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_wishbone
 
  component neorv32_wishbone
 
    generic (
 
    generic (
 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
 
 
 
      -- Internal instruction memory --
 
      -- Internal instruction memory --
 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
 
      -- Internal data memory --
 
      -- Internal data memory --
 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
Line 1772... Line 1757... 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
 
      -- CPU state --
 
      -- CPU state --
 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
 
      -- interrupt --
 
      -- interrupt --
 
      irq_o       : out std_ulogic; -- interrupt request
 
      irq_o       : out std_ulogic; -- interrupt request
 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
 
 
 
      -- custom io (conduit) --
 
      -- custom io (conduit) --
 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_nco
 
  component neorv32_neoled
 
    port (
 
    port (
 
      -- host access --
 
      -- host access --
 
      clk_i       : in  std_ulogic; -- global clock line
 
      clk_i       : in  std_ulogic; -- global clock line
 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
 
      rden_i      : in  std_ulogic; -- read enable
 
      rden_i      : in  std_ulogic; -- read enable
Line 1794... Line 1778... 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
 
      ack_o       : out std_ulogic; -- transfer acknowledge
 
      ack_o       : out std_ulogic; -- transfer acknowledge
 
      -- clock generator --
 
      -- clock generator --
 
      clkgen_en_o : out std_ulogic; -- enable clock generator
 
      clkgen_en_o : out std_ulogic; -- enable clock generator
 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
 
      -- NCO output --
 
      -- interrupt --
 
      nco_o       : out std_ulogic_vector(02 downto 0)
 
      irq_o       : out std_ulogic; -- interrupt request
 
 
 
      -- NEOLED output --
 
 
 
      neoled_o    : out std_ulogic -- serial async data line
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
 
  -- Component: Stream Link Interface (SLINK) -----------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_neoled
 
  component neorv32_slink
 
 
 
    generic (
 
 
 
      SLINK_NUM_TX  : natural := 8; -- number of TX links (0..8)
 
 
 
      SLINK_NUM_RX  : natural := 8; -- number of TX links (0..8)
 
 
 
      SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
 
 
 
      SLINK_RX_FIFO : natural := 1  -- RX fifo depth, has to be a power of two
 
 
 
    );
 
    port (
 
    port (
 
      -- host access --
 
      -- host access --
 
      clk_i       : in  std_ulogic; -- global clock line
 
      clk_i       : in  std_ulogic; -- global clock line
 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
 
      rden_i      : in  std_ulogic; -- read enable
 
      rden_i      : in  std_ulogic; -- read enable
 
      wren_i      : in  std_ulogic; -- write enable
 
      wren_i      : in  std_ulogic; -- write enable
 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
 
      ack_o       : out std_ulogic; -- transfer acknowledge
 
      ack_o       : out std_ulogic; -- transfer acknowledge
 
      -- clock generator --
 
 
 
      clkgen_en_o : out std_ulogic; -- enable clock generator
 
 
 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
 
 
 
      -- interrupt --
 
      -- interrupt --
 
      irq_o       : out std_ulogic; -- interrupt request
 
      irq_tx_o       : out std_ulogic; -- transmission done
 
      -- NEOLED output --
 
      irq_rx_o       : out std_ulogic; -- data received
 
      neoled_o    : out std_ulogic -- serial async data line
 
      -- TX stream interfaces --
 
 
 
      slink_tx_dat_o : out sdata_8x32_t; -- output data
 
 
 
      slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
 
 
 
      slink_tx_rdy_i : in  std_ulogic_vector(7 downto 0); -- ready to send
 
 
 
      -- RX stream interfaces --
 
 
 
      slink_rx_dat_i : in  sdata_8x32_t; -- input data
 
 
 
      slink_rx_val_i : in  std_ulogic_vector(7 downto 0); -- valid input
 
 
 
      slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)  -- ready to receive
 
 
 
    );
 
 
 
  end component;
 
 
 
 
 
 
 
  -- Component: External Interrupt Controller (XIRQ) ----------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  component neorv32_xirq
 
 
 
    generic (
 
 
 
      XIRQ_NUM_CH           : natural := 32; -- number of external IRQ channels (0..32)
 
 
 
      XIRQ_TRIGGER_TYPE     : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
 
 
 
      XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1')  -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
 
 
 
    );
 
 
 
    port (
 
 
 
      -- host access --
 
 
 
      clk_i     : in  std_ulogic; -- global clock line
 
 
 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
 
 
 
      rden_i    : in  std_ulogic; -- read enable
 
 
 
      wren_i    : in  std_ulogic; -- write enable
 
 
 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
 
 
 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
 
 
 
      ack_o     : out std_ulogic; -- transfer acknowledge
 
 
 
      -- external interrupt lines --
 
 
 
      xirq_i    : in  std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
 
 
 
      -- CPU interrupt --
 
 
 
      cpu_irq_o : out std_ulogic
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_sysinfo
 
  component neorv32_sysinfo
 
    generic (
 
    generic (
 
      -- General --
 
      -- General --
 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
 
      INT_BOOTLOADER_EN            : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
 
      -- Internal Instruction memory --
 
      -- Internal Instruction memory --
 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
 
 
 
      -- Internal Data memory --
 
      -- Internal Data memory --
 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
 
      -- Internal Cache memory --
 
      -- Internal Cache memory --
 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
Line 1856... Line 1875... 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
 
      IO_PWM_NUM_CH        : natural := 4;      -- number of PWM channels to implement
 
      IO_PWM_NUM_CH        : natural := 4;      -- number of PWM channels to implement
 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
 
      IO_NCO_EN            : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
 
      IO_SLINK_EN          : boolean := true;   -- implement stream link interface?
 
      IO_NEOLED_EN         : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
 
      IO_NEOLED_EN         : boolean := true;   -- implement NeoPixel-compatible smart LED interface (NEOLED)?
 
 
 
      IO_XIRQ_NUM_CH       : natural := 32      -- number of external interrupt (XIRQ) channels to implement
 
    );
 
    );
 
    port (
 
    port (
 
      -- host access --
 
      -- host access --
 
      clk_i  : in  std_ulogic; -- global clock line
 
      clk_i  : in  std_ulogic; -- global clock line
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
Line 1869... Line 1889... 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
 
      ack_o  : out std_ulogic  -- transfer acknowledge
 
      ack_o  : out std_ulogic  -- transfer acknowledge
 
    );
 
    );
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  -- Component: General Purpose FIFO .............................---------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  component neorv32_fifo
 
 
 
    generic (
 
 
 
      FIFO_DEPTH : natural := 4;     -- number of fifo entries; has to be a power of two; min 1
 
 
 
      FIFO_WIDTH : natural := 32;    -- size of data elements in fifo
 
 
 
      FIFO_RSYNC : boolean := false; -- false = async read; true = sync read
 
 
 
      FIFO_SAFE  : boolean := false  -- true = allow read/write only if data available
 
 
 
    );
 
 
 
    port (
 
 
 
      -- control --
 
 
 
      clk_i   : in  std_ulogic; -- clock, rising edge
 
 
 
      rstn_i  : in  std_ulogic; -- async reset, low-active
 
 
 
      clear_i : in  std_ulogic; -- sync reset, high-active
 
 
 
      -- write port --
 
 
 
      wdata_i : in  std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
 
 
 
      we_i    : in  std_ulogic; -- write enable
 
 
 
      free_o  : out std_ulogic; -- at least one entry is free when set
 
 
 
      -- read port --
 
 
 
      re_i    : in  std_ulogic; -- read enable
 
 
 
      rdata_o : out std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- read data
 
 
 
      avail_o : out std_ulogic  -- data available when set
 
 
 
    );
 
 
 
  end component;
 
 
 
 
 
  -- Component: On-Chip Debugger - Debug Module (DM) ----------------------------------------
 
  -- Component: On-Chip Debugger - Debug Module (DM) ----------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  component neorv32_debug_dm
 
  component neorv32_debug_dm
 
    port (
 
    port (
 
      -- global control --
 
      -- global control --
Line 2146... Line 2191... 
    output_v(23 downto 16) := input(15 downto 08);
 
    output_v(23 downto 16) := input(15 downto 08);
 
    output_v(31 downto 24) := input(07 downto 00);
 
    output_v(31 downto 24) := input(07 downto 00);
 
    return output_v;
 
    return output_v;
 
  end function bswap32_f;
 
  end function bswap32_f;
 
 
 
 
 
 
 
  -- Function: Convert char to lowercase ----------------------------------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  function char_tolower_f(ch : character) return character is
 
 
 
    variable res: character;
 
 
 
   begin
 
 
 
     case ch is
 
 
 
       when 'A'    => res := 'a';
 
 
 
       when 'B'    => res := 'b';
 
 
 
       when 'C'    => res := 'c';
 
 
 
       when 'D'    => res := 'd';
 
 
 
       when 'E'    => res := 'e';
 
 
 
       when 'F'    => res := 'f';
 
 
 
       when 'G'    => res := 'g';
 
 
 
       when 'H'    => res := 'h';
 
 
 
       when 'I'    => res := 'i';
 
 
 
       when 'J'    => res := 'j';
 
 
 
       when 'K'    => res := 'k';
 
 
 
       when 'L'    => res := 'l';
 
 
 
       when 'M'    => res := 'm';
 
 
 
       when 'N'    => res := 'n';
 
 
 
       when 'O'    => res := 'o';
 
 
 
       when 'P'    => res := 'p';
 
 
 
       when 'Q'    => res := 'q';
 
 
 
       when 'R'    => res := 'r';
 
 
 
       when 'S'    => res := 's';
 
 
 
       when 'T'    => res := 't';
 
 
 
       when 'U'    => res := 'u';
 
 
 
       when 'V'    => res := 'v';
 
 
 
       when 'W'    => res := 'w';
 
 
 
       when 'X'    => res := 'x';
 
 
 
       when 'Y'    => res := 'y';
 
 
 
       when 'Z'    => res := 'z';
 
 
 
       when others => res := ch;
 
 
 
      end case;
 
 
 
    return res;
 
 
 
  end function char_tolower_f;
 
 
 
 
 
 
 
  -- Function: Compare strings (convert to lower case, check lengths) -----------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  function str_equal_f(str0 : string; str1 : string) return boolean is
 
 
 
    variable tmp0_v : string(str0'range);
 
 
 
    variable tmp1_v : string(str1'range);
 
 
 
  begin
 
 
 
    if (str0'length /= str1'length) then -- equal length?
 
 
 
      return false;
 
 
 
    else
 
 
 
      -- convert to lower case --
 
 
 
      for i in str0'range loop
 
 
 
        tmp0_v(i) := char_tolower_f(str0(i));
 
 
 
      end loop;
 
 
 
      for i in str1'range loop
 
 
 
        tmp1_v(i) := char_tolower_f(str1(i));
 
 
 
      end loop;
 
 
 
      -- compare lowercase strings --
 
 
 
      if (tmp0_v = tmp1_v) then
 
 
 
        return true;
 
 
 
      else
 
 
 
        return false;
 
 
 
      end if;
 
 
 
    end if;
 
 
 
  end function str_equal_f;
 
 
 
 
 
 
 
  -- Function: Initialize mem32_t array from another mem32_t array --------------------------
 
 
 
  -- -------------------------------------------------------------------------------------------
 
 
 
  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
 
 
 
  impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t is
 
 
 
    variable mem_v : mem32_t(0 to depth-1);
 
 
 
  begin
 
 
 
      mem_v := (others => (others => '0')); -- make sure remaining memory entries are set to zero
 
 
 
      if (init'length > depth) then
 
 
 
        return mem_v;
 
 
 
      end if;
 
 
 
      for idx_v in 0 to init'length-1 loop -- init only in range of source data array
 
 
 
        mem_v(idx_v) := init(idx_v);
 
 
 
      end loop; -- idx_v
 
 
 
    return mem_v;
 
 
 
  end function mem32_init_f;
 
 
 
 
 
end neorv32_package;
 
end neorv32_package;
 
 
 
 
 
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