| Line 42... |
Line 42... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- external bus interface --
|
|
constant wb_pipe_mode_c : boolean := false; -- protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
|
|
constant wb_big_endian_c : boolean := false; -- byte order: true=big-endian, false=little-endian (default)
|
|
constant wb_rx_buffer_c : boolean := true; -- use register buffer for RX data when true (default)
|
|
|
|
-- CPU core --
|
-- CPU core --
|
constant ipb_entries_c : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
|
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
| Line 68... |
Line 62... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050710"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050900"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
|
|
|
|
-- External Interface Types ---------------------------------------------------------------
|
-- External Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
| Line 105... |
Line 98... |
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
|
function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
|
function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
|
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function is_power_of_two_f(input : natural) return boolean;
|
function is_power_of_two_f(input : natural) return boolean;
|
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function char_tolower_f(ch : character) return character;
|
function char_to_lower_f(ch : character) return character;
|
function str_equal_f(str0 : string; str1 : string) return boolean;
|
function str_equal_f(str0 : string; str1 : string) return boolean;
|
impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
|
impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
|
|
|
-- Internal (auto-generated) Configurations -----------------------------------------------
|
-- Internal (auto-generated) Configurations -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 208... |
Line 201... |
constant xirq_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
|
constant xirq_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
|
constant xirq_size_c : natural := 4*4; -- module's address space size in bytes
|
constant xirq_size_c : natural := 4*4; -- module's address space size in bytes
|
constant xirq_enable_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
|
constant xirq_enable_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
|
constant xirq_pending_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
|
constant xirq_pending_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
|
constant xirq_source_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
|
constant xirq_source_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
|
--constant xirq_res_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
|
--constant xirq_reserved_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
|
|
|
-- Machine System Timer (MTIME) --
|
-- Machine System Timer (MTIME) --
|
constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
|
constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
|
constant mtime_size_c : natural := 4*4; -- module's address space size in bytes
|
constant mtime_size_c : natural := 4*4; -- module's address space size in bytes
|
constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
|
constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
|
| Line 290... |
Line 283... |
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
|
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
|
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
|
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
|
constant ctrl_rf_r0_we_c : natural := 17; -- force write access and force rd=r0
|
|
-- alu --
|
-- alu --
|
constant ctrl_alu_arith_c : natural := 18; -- ALU arithmetic command
|
constant ctrl_alu_arith_c : natural := 17; -- ALU arithmetic command
|
constant ctrl_alu_logic0_c : natural := 19; -- ALU logic command bit 0
|
constant ctrl_alu_logic0_c : natural := 18; -- ALU logic command bit 0
|
constant ctrl_alu_logic1_c : natural := 20; -- ALU logic command bit 1
|
constant ctrl_alu_logic1_c : natural := 19; -- ALU logic command bit 1
|
constant ctrl_alu_func0_c : natural := 21; -- ALU function select command bit 0
|
constant ctrl_alu_func0_c : natural := 20; -- ALU function select command bit 0
|
constant ctrl_alu_func1_c : natural := 22; -- ALU function select command bit 1
|
constant ctrl_alu_func1_c : natural := 21; -- ALU function select command bit 1
|
constant ctrl_alu_addsub_c : natural := 23; -- 0=ADD, 1=SUB
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
constant ctrl_alu_opa_mux_c : natural := 24; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opb_mux_c : natural := 25; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_unsigned_c : natural := 26; -- is unsigned ALU operation
|
constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation
|
constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_ar_c : natural := 28; -- is arithmetic shift
|
constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift
|
constant ctrl_alu_frm0_c : natural := 29; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm0_c : natural := 28; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm1_c : natural := 30; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm1_c : natural := 29; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm2_c : natural := 31; -- FPU rounding mode bit 2
|
constant ctrl_alu_frm2_c : natural := 30; -- FPU rounding mode bit 2
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 32; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 33; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 34; -- read data request
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_wr_c : natural := 35; -- write data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_if_c : natural := 36; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
|
constant ctrl_bus_mo_we_c : natural := 37; -- memory address and data output register write enable
|
constant ctrl_bus_mo_we_c : natural := 36; -- memory address and data output register write enable
|
constant ctrl_bus_mi_we_c : natural := 38; -- memory data input register write enable
|
constant ctrl_bus_mi_we_c : natural := 37; -- memory data input register write enable
|
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 38; -- is unsigned load
|
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_ierr_ack_c : natural := 39; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 40; -- acknowledge data access bus exceptions
|
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 41; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 42; -- executed fencei operation
|
constant ctrl_bus_lock_c : natural := 44; -- make atomic/exclusive access lock
|
constant ctrl_bus_lock_c : natural := 43; -- make atomic/exclusive access lock
|
constant ctrl_bus_de_lock_c : natural := 45; -- remove atomic/exclusive access
|
constant ctrl_bus_de_lock_c : natural := 44; -- remove atomic/exclusive access
|
constant ctrl_bus_ch_lock_c : natural := 46; -- evaluate atomic/exclusive lock (SC operation)
|
constant ctrl_bus_ch_lock_c : natural := 45; -- evaluate atomic/exclusive lock (SC operation)
|
-- co-processors --
|
-- co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 47; -- cp select ID lsb
|
constant ctrl_cp_id_lsb_c : natural := 46; -- cp select ID lsb
|
constant ctrl_cp_id_msb_c : natural := 48; -- cp select ID msb
|
constant ctrl_cp_id_msb_c : natural := 47; -- cp select ID msb
|
-- instruction's control blocks (used by cpu co-processors) --
|
-- instruction's control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct3_0_c : natural := 49; -- funct3 bit 0
|
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0
|
constant ctrl_ir_funct3_1_c : natural := 50; -- funct3 bit 1
|
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1
|
constant ctrl_ir_funct3_2_c : natural := 51; -- funct3 bit 2
|
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2
|
constant ctrl_ir_funct12_0_c : natural := 52; -- funct12 bit 0
|
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0
|
constant ctrl_ir_funct12_1_c : natural := 53; -- funct12 bit 1
|
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1
|
constant ctrl_ir_funct12_2_c : natural := 54; -- funct12 bit 2
|
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2
|
constant ctrl_ir_funct12_3_c : natural := 55; -- funct12 bit 3
|
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3
|
constant ctrl_ir_funct12_4_c : natural := 56; -- funct12 bit 4
|
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4
|
constant ctrl_ir_funct12_5_c : natural := 57; -- funct12 bit 5
|
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5
|
constant ctrl_ir_funct12_6_c : natural := 58; -- funct12 bit 6
|
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6
|
constant ctrl_ir_funct12_7_c : natural := 59; -- funct12 bit 7
|
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7
|
constant ctrl_ir_funct12_8_c : natural := 60; -- funct12 bit 8
|
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8
|
constant ctrl_ir_funct12_9_c : natural := 61; -- funct12 bit 9
|
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9
|
constant ctrl_ir_funct12_10_c : natural := 62; -- funct12 bit 10
|
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10
|
constant ctrl_ir_funct12_11_c : natural := 63; -- funct12 bit 11
|
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11
|
constant ctrl_ir_opcode7_0_c : natural := 64; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_1_c : natural := 65; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_2_c : natural := 66; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_3_c : natural := 67; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 68; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 69; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 70; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6
|
-- CPU status --
|
-- CPU status --
|
constant ctrl_priv_lvl_lsb_c : natural := 71; -- privilege level lsb
|
constant ctrl_priv_lvl_lsb_c : natural := 70; -- privilege level lsb
|
constant ctrl_priv_lvl_msb_c : natural := 72; -- privilege level msb
|
constant ctrl_priv_lvl_msb_c : natural := 71; -- privilege level msb
|
constant ctrl_sleep_c : natural := 73; -- set when CPU is in sleep mode
|
constant ctrl_sleep_c : natural := 72; -- set when CPU is in sleep mode
|
constant ctrl_trap_c : natural := 74; -- set when CPU is entering trap execution
|
constant ctrl_trap_c : natural := 73; -- set when CPU is entering trap execution
|
constant ctrl_debug_running_c : natural := 75; -- CPU is in debug mode when set
|
constant ctrl_debug_running_c : natural := 74; -- CPU is in debug mode when set
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 76; -- control bus size
|
constant ctrl_width_c : natural := 75; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 513... |
Line 505... |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300";
|
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300";
|
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301";
|
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301";
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304";
|
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304";
|
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305";
|
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305";
|
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306";
|
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306";
|
|
--
|
|
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310";
|
-- machine counter setup --
|
-- machine counter setup --
|
constant csr_cnt_setup_c : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup
|
constant csr_cnt_setup_c : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup
|
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320";
|
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320";
|
constant csr_mhpmevent3_c : std_ulogic_vector(11 downto 0) := x"323";
|
constant csr_mhpmevent3_c : std_ulogic_vector(11 downto 0) := x"323";
|
constant csr_mhpmevent4_c : std_ulogic_vector(11 downto 0) := x"324";
|
constant csr_mhpmevent4_c : std_ulogic_vector(11 downto 0) := x"324";
|
| Line 721... |
Line 715... |
-- machine information registers --
|
-- machine information registers --
|
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11";
|
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11";
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
|
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
|
-- <<< custom (NEORV32-specific) read-only CSRs >>> --
|
-- <<< custom (NEORV32-specific) read-only CSRs >>> --
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
|
|
-- Co-Processor IDs -----------------------------------------------------------------------
|
-- Co-Processor IDs -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 874... |
Line 869... |
-- Component: NEORV32 Processor Top Entity ------------------------------------------------
|
-- Component: NEORV32 Processor Top Entity ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_top
|
component neorv32_top
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- On-Chip Debugger (OCD) --
|
-- On-Chip Debugger (OCD) --
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
| Line 894... |
Line 889... |
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
|
-- Internal Instruction memory (IMEM) --
|
-- Internal Instruction memory (IMEM) --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
-- Internal Data memory (DMEM) --
|
-- Internal Data memory (DMEM) --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- Internal Cache memory (iCACHE) --
|
-- Internal Cache memory (iCACHE) --
|
ICACHE_EN : boolean := false; -- implement instruction cache
|
ICACHE_EN : boolean := false; -- implement instruction cache
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
-- External memory interface (WISHBONE) --
|
-- External memory interface (WISHBONE) --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
|
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
|
|
MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
|
|
MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
|
|
MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
|
-- Stream link interface (SLINK) --
|
-- Stream link interface (SLINK) --
|
SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
|
SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
|
SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
|
SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
|
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
|
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
|
SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
|
SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
|
-- External Interrupts Controller (XIRQ) --
|
-- External Interrupts Controller (XIRQ) --
|
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
|
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
|
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
|
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
|
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
|
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
|
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
|
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
|
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
|
IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
|
IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
-- JTAG on-chip debugger interface --
|
-- JTAG on-chip debugger interface --
|
jtag_trst_i : in std_ulogic := '0'; -- low-active TAP reset (optional)
|
jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
|
jtag_tck_i : in std_ulogic := '0'; -- serial clock
|
jtag_tck_i : in std_ulogic := 'U'; -- serial clock
|
jtag_tdi_i : in std_ulogic := '0'; -- serial data input
|
jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
|
jtag_tdo_o : out std_ulogic; -- serial data output
|
jtag_tdo_o : out std_ulogic; -- serial data output
|
jtag_tms_i : in std_ulogic := '0'; -- mode select
|
jtag_tms_i : in std_ulogic := 'U'; -- mode select
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := 'L'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
slink_tx_dat_o : out sdata_8x32_t; -- output data
|
slink_tx_dat_o : out sdata_8x32_t; -- output data
|
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
|
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
|
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- ready to send
|
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
|
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
slink_rx_dat_i : in sdata_8x32_t := (others => (others => '0')); -- input data
|
slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
|
slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- valid input
|
slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
|
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
|
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
|
-- GPIO (available if IO_GPIO_EN = true) --
|
-- GPIO (available if IO_GPIO_EN = true) --
|
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
|
uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
|
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
|
uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
|
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
-- SPI (available if IO_SPI_EN = true) --
|
-- SPI (available if IO_SPI_EN = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_EN = true) --
|
-- TWI (available if IO_TWI_EN = true) --
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
|
-- Custom Functions Subsystem IO --
|
-- Custom Functions Subsystem IO --
|
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
|
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
|
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
neoled_o : out std_ulogic; -- async serial data line
|
neoled_o : out std_ulogic; -- async serial data line
|
-- System time --
|
-- System time --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
|
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
|
-- CPU Interrupts --
|
-- CPU Interrupts --
|
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
|
nm_irq_i : in std_ulogic := 'L'; -- non-maskable interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
|
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
|
-- instruction bus interface --
|
-- instruction bus interface --
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- non-maskable interrupt --
|
-- non-maskable interrupt --
|
nm_irq_i : in std_ulogic := '0'; -- NMI
|
nm_irq_i : in std_ulogic; -- NMI
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
|
firq_i : in std_ulogic_vector(15 downto 0);
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i : in std_ulogic := '0'
|
db_halt_req_i : in std_ulogic
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_control
|
component neorv32_cpu_control
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1167... |
Line 1169... |
|
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_regfile
|
component neorv32_cpu_regfile
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension?
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
| Line 1188... |
Line 1190... |
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_alu
|
component neorv32_cpu_alu
|
generic (
|
generic (
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1220... |
Line 1222... |
|
|
-- Component: CPU Co-Processor SHIFTER ----------------------------------------------------
|
-- Component: CPU Co-Processor SHIFTER ----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_cp_shifter
|
component neorv32_cpu_cp_shifter
|
generic (
|
generic (
|
FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1242... |
Line 1244... |
|
|
-- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
|
-- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_cp_muldiv
|
component neorv32_cpu_cp_muldiv
|
generic (
|
generic (
|
FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
|
FAST_MUL_EN : boolean; -- use DSPs for faster multiplication
|
DIVISION_EN : boolean := true -- implement divider hardware
|
DIVISION_EN : boolean -- implement divider hardware
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1284... |
Line 1286... |
|
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024 -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 1347... |
Line 1349... |
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_bus_keeper is
|
component neorv32_bus_keeper is
|
generic (
|
generic (
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean; -- implement external memory bus interface?
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural -- size of processor-internal data memory in bytes
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
| Line 1372... |
Line 1374... |
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_icache
|
component neorv32_icache
|
generic (
|
generic (
|
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural; -- number of blocks (min 1), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural; -- block size in bytes (min 4), has to be a power of 2
|
ICACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_NUM_SETS : natural -- associativity / number of sets (1=direct_mapped), has to be a power of 2
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1406... |
Line 1408... |
|
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_busswitch
|
component neorv32_busswitch
|
generic (
|
generic (
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
PORT_CA_READ_ONLY : boolean; -- set if controller port A is read-only
|
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
|
PORT_CB_READ_ONLY : boolean -- set if controller port B is read-only
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1463... |
Line 1465... |
|
|
-- Component: Processor-internal instruction memory (IMEM) --------------------------------
|
-- Component: Processor-internal instruction memory (IMEM) --------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_imem
|
component neorv32_imem
|
generic (
|
generic (
|
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
|
IMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address
|
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
|
IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes
|
IMEM_AS_IROM : boolean := false -- implement IMEM as pre-initialized read-only memory?
|
IMEM_AS_IROM : boolean -- implement IMEM as pre-initialized read-only memory?
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
| Line 1483... |
Line 1485... |
|
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_dmem
|
component neorv32_dmem
|
generic (
|
generic (
|
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
|
DMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address
|
DMEM_SIZE : natural := 4*1024 -- processor-internal instruction memory size in bytes
|
DMEM_SIZE : natural -- processor-internal instruction memory size in bytes
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
| Line 1502... |
Line 1504... |
|
|
-- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
|
-- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_boot_rom
|
component neorv32_boot_rom
|
generic (
|
generic (
|
BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000" -- boot ROM base address
|
BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1576... |
Line 1578... |
|
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_uart
|
component neorv32_uart
|
generic (
|
generic (
|
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
|
UART_PRIMARY : boolean -- true = primary UART (UART0), false = secondary UART (UART1)
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1654... |
Line 1656... |
|
|
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
|
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_pwm
|
component neorv32_pwm
|
generic (
|
generic (
|
NUM_CHANNELS : natural := 4 -- number of PWM channels (0..60)
|
NUM_CHANNELS : natural -- number of PWM channels (0..60)
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1693... |
Line 1695... |
-- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
|
-- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_wishbone
|
component neorv32_wishbone
|
generic (
|
generic (
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
|
-- Bus Timeout --
|
-- Interface Configuration --
|
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
BUS_TIMEOUT : natural; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
PIPE_MODE : boolean; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
|
|
BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
|
|
ASYNC_RX : boolean -- use register buffer for RX data when false
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
| Line 1737... |
Line 1742... |
-- Component: Custom Functions Subsystem (CFS) --------------------------------------------
|
-- Component: Custom Functions Subsystem (CFS) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cfs
|
component neorv32_cfs
|
generic (
|
generic (
|
CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
|
CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
|
CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
CFS_IN_SIZE : positive; -- size of CFS input conduit in bits
|
CFS_OUT_SIZE : positive := 32 -- size of CFS output conduit in bits
|
CFS_OUT_SIZE : positive -- size of CFS output conduit in bits
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
|
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
|
| Line 1766... |
Line 1771... |
end component;
|
end component;
|
|
|
-- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
|
-- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_neoled
|
component neorv32_neoled
|
|
generic (
|
|
FIFO_DEPTH : natural -- TX FIFO depth (1..32k, power of two)
|
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
| Line 1789... |
Line 1797... |
|
|
-- Component: Stream Link Interface (SLINK) -----------------------------------------------
|
-- Component: Stream Link Interface (SLINK) -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_slink
|
component neorv32_slink
|
generic (
|
generic (
|
SLINK_NUM_TX : natural := 8; -- number of TX links (0..8)
|
SLINK_NUM_TX : natural; -- number of TX links (0..8)
|
SLINK_NUM_RX : natural := 8; -- number of TX links (0..8)
|
SLINK_NUM_RX : natural; -- number of TX links (0..8)
|
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
|
SLINK_TX_FIFO : natural; -- TX fifo depth, has to be a power of two
|
SLINK_RX_FIFO : natural := 1 -- RX fifo depth, has to be a power of two
|
SLINK_RX_FIFO : natural -- RX fifo depth, has to be a power of two
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1821... |
Line 1829... |
|
|
-- Component: External Interrupt Controller (XIRQ) ----------------------------------------
|
-- Component: External Interrupt Controller (XIRQ) ----------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_xirq
|
component neorv32_xirq
|
generic (
|
generic (
|
XIRQ_NUM_CH : natural := 32; -- number of external IRQ channels (0..32)
|
XIRQ_NUM_CH : natural; -- number of external IRQ channels (0..32)
|
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
|
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge
|
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1') -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1846... |
Line 1854... |
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_sysinfo
|
component neorv32_sysinfo
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
|
-- Internal Cache memory --
|
-- Internal Cache memory --
|
ICACHE_EN : boolean := true; -- implement instruction cache
|
ICACHE_EN : boolean; -- implement instruction cache
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
|
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean; -- implement external memory bus interface?
|
|
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
|
-- On-Chip Debugger --
|
-- On-Chip Debugger --
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement OCD?
|
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
|
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement
|
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
|
IO_CFS_EN : boolean := true; -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
|
IO_SLINK_EN : boolean := true; -- implement stream link interface?
|
IO_SLINK_EN : boolean; -- implement stream link interface?
|
IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_XIRQ_NUM_CH : natural := 32 -- number of external interrupt (XIRQ) channels to implement
|
IO_XIRQ_NUM_CH : natural -- number of external interrupt (XIRQ) channels to implement
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1889... |
Line 1898... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: General Purpose FIFO .............................---------------------------
|
-- Component: General Purpose FIFO --------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_fifo
|
component neorv32_fifo
|
generic (
|
generic (
|
FIFO_DEPTH : natural := 4; -- number of fifo entries; has to be a power of two; min 1
|
FIFO_DEPTH : natural; -- number of fifo entries; has to be a power of two; min 1
|
FIFO_WIDTH : natural := 32; -- size of data elements in fifo
|
FIFO_WIDTH : natural; -- size of data elements in fifo
|
FIFO_RSYNC : boolean := false; -- false = async read; true = sync read
|
FIFO_RSYNC : boolean; -- false = async read; true = sync read
|
FIFO_SAFE : boolean := false -- true = allow read/write only if data available
|
FIFO_SAFE : boolean -- true = allow read/write only if entry available
|
);
|
);
|
port (
|
port (
|
-- control --
|
-- control --
|
clk_i : in std_ulogic; -- clock, rising edge
|
clk_i : in std_ulogic; -- clock, rising edge
|
rstn_i : in std_ulogic; -- async reset, low-active
|
rstn_i : in std_ulogic; -- async reset, low-active
|
clear_i : in std_ulogic; -- sync reset, high-active
|
clear_i : in std_ulogic; -- sync reset, high-active
|
|
level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
|
-- write port --
|
-- write port --
|
wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
|
we_i : in std_ulogic; -- write enable
|
we_i : in std_ulogic; -- write enable
|
free_o : out std_ulogic; -- at least one entry is free when set
|
free_o : out std_ulogic; -- at least one entry is free when set
|
-- read port --
|
-- read port --
|
| Line 1949... |
Line 1959... |
|
|
-- Component: On-Chip Debugger - Debug Transport Module (DTM) -----------------------------
|
-- Component: On-Chip Debugger - Debug Transport Module (DTM) -----------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_debug_dtm
|
component neorv32_debug_dtm
|
generic (
|
generic (
|
IDCODE_VERSION : std_ulogic_vector(03 downto 0) := x"0"; -- version
|
IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
|
IDCODE_PARTID : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
|
IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number
|
IDCODE_MANID : std_ulogic_vector(10 downto 0) := "00000000000" -- manufacturer id
|
IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
| Line 2193... |
Line 2203... |
return output_v;
|
return output_v;
|
end function bswap32_f;
|
end function bswap32_f;
|
|
|
-- Function: Convert char to lowercase ----------------------------------------------------
|
-- Function: Convert char to lowercase ----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function char_tolower_f(ch : character) return character is
|
function char_to_lower_f(ch : character) return character is
|
variable res: character;
|
variable res: character;
|
begin
|
begin
|
case ch is
|
case ch is
|
when 'A' => res := 'a';
|
when 'A' => res := 'a';
|
when 'B' => res := 'b';
|
when 'B' => res := 'b';
|
| Line 2226... |
Line 2236... |
when 'Y' => res := 'y';
|
when 'Y' => res := 'y';
|
when 'Z' => res := 'z';
|
when 'Z' => res := 'z';
|
when others => res := ch;
|
when others => res := ch;
|
end case;
|
end case;
|
return res;
|
return res;
|
end function char_tolower_f;
|
end function char_to_lower_f;
|
|
|
-- Function: Compare strings (convert to lower case, check lengths) -----------------------
|
-- Function: Compare strings (convert to lower case, check lengths) -----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function str_equal_f(str0 : string; str1 : string) return boolean is
|
function str_equal_f(str0 : string; str1 : string) return boolean is
|
variable tmp0_v : string(str0'range);
|
variable tmp0_v : string(str0'range);
|
| Line 2239... |
Line 2249... |
if (str0'length /= str1'length) then -- equal length?
|
if (str0'length /= str1'length) then -- equal length?
|
return false;
|
return false;
|
else
|
else
|
-- convert to lower case --
|
-- convert to lower case --
|
for i in str0'range loop
|
for i in str0'range loop
|
tmp0_v(i) := char_tolower_f(str0(i));
|
tmp0_v(i) := char_to_lower_f(str0(i));
|
end loop;
|
end loop;
|
for i in str1'range loop
|
for i in str1'range loop
|
tmp1_v(i) := char_tolower_f(str1(i));
|
tmp1_v(i) := char_to_lower_f(str1(i));
|
end loop;
|
end loop;
|
-- compare lowercase strings --
|
-- compare lowercase strings --
|
if (tmp0_v = tmp1_v) then
|
if (tmp0_v = tmp1_v) then
|
return true;
|
return true;
|
else
|
else
|
| Line 2269... |
Line 2279... |
mem_v(idx_v) := init(idx_v);
|
mem_v(idx_v) := init(idx_v);
|
end loop; -- idx_v
|
end loop; -- idx_v
|
return mem_v;
|
return mem_v;
|
end function mem32_init_f;
|
end function mem32_init_f;
|
|
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
No newline at end of file
|
No newline at end of file
|
