| Line 62... |
Line 62... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060301"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060400"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- External Interface Types ---------------------------------------------------------------
|
-- External Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
| Line 314... |
Line 314... |
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
|
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
|
-- alu --
|
-- alu --
|
constant ctrl_alu_arith_c : natural := 17; -- ALU arithmetic command
|
constant ctrl_alu_op0_c : natural := 17; -- ALU operation select bit 0
|
constant ctrl_alu_logic0_c : natural := 18; -- ALU logic command bit 0
|
constant ctrl_alu_op1_c : natural := 18; -- ALU operation select bit 1
|
constant ctrl_alu_logic1_c : natural := 19; -- ALU logic command bit 1
|
constant ctrl_alu_op2_c : natural := 19; -- ALU operation select bit 2
|
constant ctrl_alu_func0_c : natural := 20; -- ALU function select command bit 0
|
constant ctrl_alu_func0_c : natural := 20; -- ALU function select command bit 0
|
constant ctrl_alu_func1_c : natural := 21; -- ALU function select command bit 1
|
constant ctrl_alu_func1_c : natural := 21; -- ALU function select command bit 1
|
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB
|
constant ctrl_alu_opa_mux_c : natural := 22; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opb_mux_c : natural := 23; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_unsigned_c : natural := 24; -- is unsigned ALU operation
|
constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation
|
constant ctrl_alu_shift_dir_c : natural := 25; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_ar_c : natural := 26; -- is arithmetic shift
|
constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift
|
constant ctrl_alu_frm0_c : natural := 27; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm0_c : natural := 28; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm1_c : natural := 28; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm1_c : natural := 29; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm2_c : natural := 29; -- FPU rounding mode bit 2
|
constant ctrl_alu_frm2_c : natural := 30; -- FPU rounding mode bit 2
|
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_rd_c : natural := 32; -- read data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_wr_c : natural := 33; -- write data request
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 34; -- instruction fetch request
|
constant ctrl_bus_mo_we_c : natural := 36; -- memory address and data output register write enable
|
constant ctrl_bus_mo_we_c : natural := 35; -- memory address and data output register write enable
|
constant ctrl_bus_mi_we_c : natural := 37; -- memory data input register write enable
|
constant ctrl_bus_mi_we_c : natural := 36; -- memory data input register write enable
|
constant ctrl_bus_unsigned_c : natural := 38; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load
|
constant ctrl_bus_ierr_ack_c : natural := 39; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 40; -- acknowledge data access bus exceptions
|
constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions
|
constant ctrl_bus_fence_c : natural := 41; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 40; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 42; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation
|
constant ctrl_bus_lock_c : natural := 43; -- make atomic/exclusive access lock
|
constant ctrl_bus_lock_c : natural := 42; -- make atomic/exclusive access lock
|
constant ctrl_bus_de_lock_c : natural := 44; -- remove atomic/exclusive access
|
constant ctrl_bus_de_lock_c : natural := 43; -- remove atomic/exclusive access
|
constant ctrl_bus_ch_lock_c : natural := 45; -- evaluate atomic/exclusive lock (SC operation)
|
constant ctrl_bus_ch_lock_c : natural := 44; -- evaluate atomic/exclusive lock (SC operation)
|
-- co-processors --
|
-- co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 46; -- cp select ID lsb
|
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select ID lsb
|
constant ctrl_cp_id_msb_c : natural := 47; -- cp select ID msb
|
constant ctrl_cp_id_msb_c : natural := 46; -- cp select ID msb
|
-- instruction's control blocks (used by cpu co-processors) --
|
-- instruction's control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0
|
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
|
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1
|
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
|
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2
|
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
|
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0
|
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
|
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1
|
constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1
|
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2
|
constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2
|
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3
|
constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3
|
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4
|
constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4
|
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5
|
constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5
|
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6
|
constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6
|
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7
|
constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7
|
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8
|
constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8
|
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9
|
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9
|
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10
|
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
|
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11
|
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
|
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
-- CPU status --
|
-- CPU status --
|
constant ctrl_priv_lvl_lsb_c : natural := 70; -- privilege level lsb
|
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb
|
constant ctrl_priv_lvl_msb_c : natural := 71; -- privilege level msb
|
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb
|
constant ctrl_sleep_c : natural := 72; -- set when CPU is in sleep mode
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
constant ctrl_trap_c : natural := 73; -- set when CPU is entering trap execution
|
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
|
constant ctrl_debug_running_c : natural := 74; -- CPU is in debug mode when set
|
constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 75; -- control bus size
|
constant ctrl_width_c : natural := 74; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 524... |
Line 523... |
|
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- <<< standard read/write CSRs >>> --
|
-- <<< standard read/write CSRs >>> --
|
-- user floating-point CSRs --
|
-- user floating-point CSRs --
|
constant csr_class_float_c : std_ulogic_vector(07 downto 0) := x"00"; -- floating point
|
constant csr_class_float_c : std_ulogic_vector(09 downto 0) := x"00" & "00"; -- floating point
|
constant csr_fflags_c : std_ulogic_vector(11 downto 0) := x"001";
|
constant csr_fflags_c : std_ulogic_vector(11 downto 0) := x"001";
|
constant csr_frm_c : std_ulogic_vector(11 downto 0) := x"002";
|
constant csr_frm_c : std_ulogic_vector(11 downto 0) := x"002";
|
constant csr_fcsr_c : std_ulogic_vector(11 downto 0) := x"003";
|
constant csr_fcsr_c : std_ulogic_vector(11 downto 0) := x"003";
|
-- machine trap setup --
|
-- machine trap setup --
|
constant csr_class_setup_c : std_ulogic_vector(08 downto 0) := x"30" & '0'; -- trap setup
|
constant csr_class_setup_c : std_ulogic_vector(08 downto 0) := x"30" & '0'; -- trap setup
|
| Line 574... |
Line 573... |
constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c";
|
constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c";
|
constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d";
|
constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d";
|
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
|
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
|
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
|
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
|
-- machine trap handling --
|
-- machine trap handling --
|
constant csr_class_trap_c : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
|
constant csr_class_trap_c : std_ulogic_vector(08 downto 0) := x"34" & '0'; -- machine trap handling
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
| Line 759... |
Line 758... |
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extensions)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extensions)
|
constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension)
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- arithmetic core --
|
-- ALU core [DO NOT CHANGE ENCODING!] --
|
constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
|
constant alu_op_add_c : std_ulogic_vector(2 downto 0) := "000"; -- alu_result <= A + B
|
constant alu_arith_cmd_slt_c : std_ulogic := '1'; -- r.arith <= A < B
|
constant alu_op_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- alu_result <= A - B
|
-- logic core --
|
--constant alu_op_mova_c : std_ulogic_vector(2 downto 0) := "010"; -- alu_result <= A (rs1)
|
constant alu_logic_cmd_movb_c : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
|
constant alu_op_slt_c : std_ulogic_vector(2 downto 0) := "011"; -- alu_result <= A < B
|
constant alu_logic_cmd_xor_c : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
|
constant alu_op_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- alu_result <= B
|
constant alu_logic_cmd_or_c : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
|
constant alu_op_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- alu_result <= A xor B
|
constant alu_logic_cmd_and_c : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
|
constant alu_op_or_c : std_ulogic_vector(2 downto 0) := "110"; -- alu_result <= A or B
|
-- function select (actual alu result) --
|
constant alu_op_and_c : std_ulogic_vector(2 downto 0) := "111"; -- alu_result <= A and B
|
constant alu_func_cmd_arith_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
|
-- function select (actual ALU result) --
|
constant alu_func_cmd_logic_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
|
constant alu_func_core_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= alu_result
|
constant alu_func_cmd_csrr_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= CSR read
|
constant alu_func_nxpc_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= next_PC
|
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
|
constant alu_func_csrr_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= CSR read
|
|
constant alu_func_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
| Line 1175... |
Line 1175... |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
-- data output --
|
-- data output --
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to next instruction)
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- FPU interface --
|
-- FPU interface --
|
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
|
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i : in std_ulogic;
|
db_halt_req_i : in std_ulogic;
|
| Line 1242... |
Line 1243... |
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- data output --
|
-- data output --
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
| Line 1406... |
Line 1408... |
end component;
|
end component;
|
|
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_bus_keeper is
|
component neorv32_bus_keeper is
|
generic (
|
|
-- External memory interface --
|
|
MEM_EXT_EN : boolean; -- implement external memory bus interface?
|
|
-- Internal instruction memory --
|
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
|
-- Internal data memory --
|
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural -- size of processor-internal data memory in bytes
|
|
);
|
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
| Line 1431... |
Line 1423... |
-- bus monitoring --
|
-- bus monitoring --
|
bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
bus_rden_i : in std_ulogic; -- read enable
|
bus_rden_i : in std_ulogic; -- read enable
|
bus_wren_i : in std_ulogic; -- write enable
|
bus_wren_i : in std_ulogic; -- write enable
|
bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
|
bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
|
bus_err_i : in std_ulogic -- transfer error from bus system
|
bus_err_i : in std_ulogic; -- transfer error from bus system
|
|
bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
|
|
bus_ext_i : in std_ulogic -- external bus access
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1788... |
Line 1782... |
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
lock_i : in std_ulogic; -- exclusive access request
|
lock_i : in std_ulogic; -- exclusive access request
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
|
tmo_o : out std_ulogic; -- transfer timeout
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
|
ext_o : out std_ulogic; -- active external access
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
| Line 1822... |
Line 1818... |
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- word write enable
|
wren_i : in std_ulogic; -- word write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
err_o : out std_ulogic; -- transfer error
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic; -- interrupt request
|
irq_o : out std_ulogic; -- interrupt request
|
