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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Main VHDL package file >> #
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-- # << NEORV32 - Main VHDL package file >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060500"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060600"; -- no touchy!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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-- Check if we're inside the Matrix -------------------------------------------------------
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-- Check if we're inside the Matrix -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant is_simulation_c : boolean := false -- seems like we're on real hardware
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constant is_simulation_c : boolean := false -- seems like we're on real hardware
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function leading_zeros_f(input : std_ulogic_vector) return natural;
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function leading_zeros_f(input : std_ulogic_vector) return natural;
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impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
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impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
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-- Internal (auto-generated) Configurations -----------------------------------------------
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-- Internal (auto-generated) Configurations -----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
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constant def_rst_val_c : std_ulogic; -- Use a deferred constant, prevents compile error with Questa, see IEEE 1076-2008 14.4.2.1
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
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-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant dm_pbuf_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";
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constant dm_pbuf_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";
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constant dm_data_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";
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constant dm_data_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";
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constant dm_sreg_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";
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constant dm_sreg_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";
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-- IO: Peripheral Devices ("IO") Area --
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-- IO: Peripheral Devices ("IO") Area --
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-- Control register(s) (including the device-enable) should be located at the base address of each device
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-- Control register(s) (including the device-enable flag) should be located at the base address of each device
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00";
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constant io_size_c : natural := 512; -- IO address space size in bytes, fixed!
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constant io_size_c : natural := 512; -- IO address space size in bytes, fixed!
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-- Custom Functions Subsystem (CFS) --
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-- Custom Functions Subsystem (CFS) --
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constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address
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constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address
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-- reserved --
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-- reserved --
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--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
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--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
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--constant reserved_size_c : natural := 16*4; -- module's address space size in bytes
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--constant reserved_size_c : natural := 16*4; -- module's address space size in bytes
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-- Execute In Place Module (XIP) --
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constant xip_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; -- base address
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constant xip_size_c : natural := 4*4; -- module's address space size in bytes
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constant xip_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40";
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constant xip_map_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44";
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constant xip_data_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48";
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constant xip_data_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4C";
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-- reserved --
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-- reserved --
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--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; -- base address
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--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50"; -- base address
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--constant reserved_size_c : natural := 8*4; -- module's address space size in bytes
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--constant reserved_size_c : natural := 4*4; -- module's address space size in bytes
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-- General Purpose Timer (GPTMR) --
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-- General Purpose Timer (GPTMR) --
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constant gptmr_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60"; -- base address
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constant gptmr_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60"; -- base address
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constant gptmr_size_c : natural := 4*4; -- module's address space size in bytes
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constant gptmr_size_c : natural := 4*4; -- module's address space size in bytes
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constant gptmr_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";
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constant gptmr_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";
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MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory (DMEM) --
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory (iCACHE) --
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-- Internal Instruction Cache (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface (WISHBONE) --
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-- External memory interface (WISHBONE) --
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean := false -- implement execute in place module (XIP)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge
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wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge
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wb_err_i : in std_ulogic := 'L'; -- transfer error
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wb_err_i : in std_ulogic := 'L'; -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o : out std_ulogic; -- chip-select, low-active
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xip_clk_o : out std_ulogic; -- serial clock
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xip_sdi_i : in std_ulogic := 'L'; -- device data input
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xip_sdo_o : out std_ulogic; -- controller data output
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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-- TWI (available if IO_TWI_EN = true) --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io : inout std_logic := 'U'; -- twi serial data line
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twi_sda_io : inout std_logic := 'U'; -- twi serial data line
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twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
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twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
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pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
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-- Custom Functions Subsystem IO --
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-- Custom Functions Subsystem IO --
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_ulogic; -- async serial data line
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neoled_o : out std_ulogic; -- async serial data line
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-- System time --
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-- System time --
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
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xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels
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-- CPU Interrupts --
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-- CPU Interrupts --
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mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
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mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
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msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
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mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
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mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
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);
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);
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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-- bus monitoring --
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-- bus monitoring --
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_rden_i : in std_ulogic; -- read enable
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bus_rden_i : in std_ulogic; -- read enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_err_i : in std_ulogic; -- transfer error from bus system
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bus_err_i : in std_ulogic; -- transfer error from bus system
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bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
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bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
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bus_ext_i : in std_ulogic -- external bus access
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bus_ext_i : in std_ulogic; -- external bus access
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bus_xip_i : in std_ulogic -- pending XIP access
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);
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);
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end component;
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end component;
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-- Component: CPU Instruction Cache -------------------------------------------------------
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-- Component: CPU Instruction Cache -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 1523... |
Line 1539... |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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p_bus_err_i : in std_ulogic -- bus transfer error
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p_bus_err_i : in std_ulogic -- bus transfer error
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);
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);
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end component;
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end component;
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-- Component: CPU Compressed Instructions Decompressor ------------------------------------
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-- Component: CPU Compressed Instructions De-Compressor -----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_decompressor
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component neorv32_cpu_decompressor
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port (
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port (
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-- instruction input --
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-- instruction input --
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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| Line 1620... |
Line 1636... |
rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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-- parallel io --
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-- parallel io --
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gpio_o : out std_ulogic_vector(63 downto 0);
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gpio_o : out std_ulogic_vector(63 downto 0);
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gpio_i : in std_ulogic_vector(63 downto 0)
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gpio_i : in std_ulogic_vector(63 downto 0)
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);
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);
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end component;
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end component;
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| Line 1752... |
Line 1769... |
ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- pwm output channels --
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-- pwm output channels --
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pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
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pwm_o : out std_ulogic_vector(59 downto 0)
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);
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);
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end component;
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end component;
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|
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-- Component: True Random Number Generator (TRNG) -----------------------------------------
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-- Component: True Random Number Generator (TRNG) -----------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 1805... |
Line 1822... |
ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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tmo_o : out std_ulogic; -- transfer timeout
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tmo_o : out std_ulogic; -- transfer timeout
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priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
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priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
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ext_o : out std_ulogic; -- active external access
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ext_o : out std_ulogic; -- active external access
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-- xip configuration --
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xip_en_i : in std_ulogic; -- XIP module enabled
|
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xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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| Line 1925... |
Line 1945... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- external interrupt lines --
|
-- external interrupt lines --
|
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
|
xirq_i : in std_ulogic_vector(31 downto 0);
|
-- CPU interrupt --
|
-- CPU interrupt --
|
cpu_irq_o : out std_ulogic
|
cpu_irq_o : out std_ulogic
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 1951... |
Line 1971... |
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic -- transmission done interrupt
|
irq_o : out std_ulogic -- transmission done interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Component: Execute In Place Module (XIP) -----------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_xip
|
|
port (
|
|
-- globals --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
|
-- host access: control register access port --
|
|
ct_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
ct_rden_i : in std_ulogic; -- read enable
|
|
ct_wren_i : in std_ulogic; -- write enable
|
|
ct_data_i : in std_ulogic_vector(31 downto 0); -- data in
|
|
ct_data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
ct_ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- host access: instruction fetch access port (read-only) --
|
|
if_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
if_rden_i : in std_ulogic; -- read enable
|
|
if_data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
if_ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- status --
|
|
xip_en_o : out std_ulogic; -- XIP enable
|
|
xip_acc_o : out std_ulogic; -- pending XIP access
|
|
xip_page_o : out std_ulogic_vector(03 downto 0); -- XIP page
|
|
-- clock generator --
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
|
-- SPI device interface --
|
|
spi_csn_o : out std_ulogic; -- chip-select, low-active
|
|
spi_clk_o : out std_ulogic; -- serial clock
|
|
spi_data_i : in std_ulogic; -- device data output
|
|
spi_data_o : out std_ulogic -- controller data output
|
|
);
|
|
end component;
|
|
|
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_sysinfo
|
component neorv32_sysinfo
|
generic (
|
generic (
|
-- General --
|
-- General --
|
| Line 2002... |
Line 2056... |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
|
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
|
IO_SLINK_EN : boolean; -- implement stream link interface?
|
IO_SLINK_EN : boolean; -- implement stream link interface?
|
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
|
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
|
IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)?
|
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
|
|
IO_XIP_EN : boolean -- implement execute in place module (XIP)?
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
|
wren_i : in std_ulogic; -- write enable
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
err_o : out std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: General Purpose FIFO --------------------------------------------------------
|
-- Component: General Purpose FIFO --------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 2421... |
Line 2478... |
end loop; -- idx_v
|
end loop; -- idx_v
|
return mem_v;
|
return mem_v;
|
end function mem32_init_f;
|
end function mem32_init_f;
|
|
|
|
|
|
-- Finally set deferred constant, see IEEE 1076-2008 14.4.2.1 (NEORV32 Issue #242) --------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
|
|
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
No newline at end of file
|
No newline at end of file
|
