| Line 42... |
Line 42... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- use dedicated hardware reset value for UNCRITICAL registers --
|
-- use dedicated hardware reset value for UNCRITICAL CPU registers --
|
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
|
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
|
constant dedicated_reset_c : boolean := false;
|
constant dedicated_reset_c : boolean := false;
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
| Line 63... |
Line 63... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060800"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060900"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
| Line 87... |
Line 87... |
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
|
|
-- Internal Interface Types ---------------------------------------------------------------
|
-- Internal Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
|
type pmp_ctrl_if_t is array (0 to 15) of std_ulogic_vector(07 downto 0);
|
type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
|
type pmp_addr_if_t is array (0 to 15) of std_ulogic_vector(33 downto 2); -- bits 33:2 of phys. address
|
|
|
-- Internal Memory Types Configuration Types ----------------------------------------------
|
-- Internal Memory Types Configuration Types ----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries
|
type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries
|
type mem8_t is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries
|
type mem8_t is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries
|
| Line 320... |
Line 320... |
constant sysinfo_size_c : natural := 8*4; -- module's address space size in bytes
|
constant sysinfo_size_c : natural := 8*4; -- module's address space size in bytes
|
|
|
-- Main CPU Control Bus -------------------------------------------------------------------
|
-- Main CPU Control Bus -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- register file --
|
-- register file --
|
constant ctrl_rf_in_mux_c : natural := 0; -- input source select lsb (0=MEM, 1=ALU)
|
constant ctrl_rf_wb_en_c : natural := 0; -- write back enable
|
constant ctrl_rf_rs1_adr0_c : natural := 1; -- source register 1 address bit 0
|
constant ctrl_rf_rs1_adr0_c : natural := 1; -- source register 1 address bit 0
|
constant ctrl_rf_rs1_adr1_c : natural := 2; -- source register 1 address bit 1
|
constant ctrl_rf_rs1_adr1_c : natural := 2; -- source register 1 address bit 1
|
constant ctrl_rf_rs1_adr2_c : natural := 3; -- source register 1 address bit 2
|
constant ctrl_rf_rs1_adr2_c : natural := 3; -- source register 1 address bit 2
|
constant ctrl_rf_rs1_adr3_c : natural := 4; -- source register 1 address bit 3
|
constant ctrl_rf_rs1_adr3_c : natural := 4; -- source register 1 address bit 3
|
constant ctrl_rf_rs1_adr4_c : natural := 5; -- source register 1 address bit 4
|
constant ctrl_rf_rs1_adr4_c : natural := 5; -- source register 1 address bit 4
|
| Line 336... |
Line 336... |
constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0
|
constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0
|
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
|
constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
|
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
|
constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
|
constant ctrl_rf_mux0_c : natural := 16; -- input source select lsb
|
|
constant ctrl_rf_mux1_c : natural := 17; -- input source select msb
|
-- alu --
|
-- alu --
|
constant ctrl_alu_op0_c : natural := 17; -- ALU operation select bit 0
|
constant ctrl_alu_op0_c : natural := 18; -- ALU operation select bit 0
|
constant ctrl_alu_op1_c : natural := 18; -- ALU operation select bit 1
|
constant ctrl_alu_op1_c : natural := 19; -- ALU operation select bit 1
|
constant ctrl_alu_op2_c : natural := 19; -- ALU operation select bit 2
|
constant ctrl_alu_op2_c : natural := 20; -- ALU operation select bit 2
|
constant ctrl_alu_func0_c : natural := 20; -- ALU function select command bit 0
|
constant ctrl_alu_opa_mux_c : natural := 21; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_func1_c : natural := 21; -- ALU function select command bit 1
|
constant ctrl_alu_opb_mux_c : natural := 22; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_opa_mux_c : natural := 22; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_unsigned_c : natural := 23; -- is unsigned ALU operation
|
constant ctrl_alu_opb_mux_c : natural := 23; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_shift_dir_c : natural := 24; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_unsigned_c : natural := 24; -- is unsigned ALU operation
|
constant ctrl_alu_shift_ar_c : natural := 25; -- is arithmetic shift
|
constant ctrl_alu_shift_dir_c : natural := 25; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_frm0_c : natural := 26; -- FPU rounding mode bit 0
|
constant ctrl_alu_shift_ar_c : natural := 26; -- is arithmetic shift
|
constant ctrl_alu_frm1_c : natural := 27; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm0_c : natural := 27; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm2_c : natural := 28; -- FPU rounding mode bit 2
|
constant ctrl_alu_frm1_c : natural := 28; -- FPU rounding mode bit 1
|
|
constant ctrl_alu_frm2_c : natural := 29; -- FPU rounding mode bit 2
|
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 30; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 32; -- read data request
|
constant ctrl_bus_rd_c : natural := 31; -- read data request
|
constant ctrl_bus_wr_c : natural := 33; -- write data request
|
constant ctrl_bus_wr_c : natural := 32; -- write data request
|
constant ctrl_bus_if_c : natural := 34; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 33; -- instruction fetch request
|
constant ctrl_bus_mo_we_c : natural := 35; -- memory address and data output register write enable
|
constant ctrl_bus_mo_we_c : natural := 34; -- memory address and data output register write enable
|
constant ctrl_bus_mi_we_c : natural := 36; -- memory data input register write enable
|
constant ctrl_bus_mi_we_c : natural := 35; -- memory data input register write enable
|
constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
|
constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions
|
constant ctrl_bus_fence_c : natural := 37; -- executed fence operation
|
constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions
|
constant ctrl_bus_fencei_c : natural := 38; -- executed fencei operation
|
constant ctrl_bus_fence_c : natural := 40; -- executed fence operation
|
constant ctrl_bus_lock_c : natural := 39; -- make atomic/exclusive access lock
|
constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation
|
constant ctrl_bus_de_lock_c : natural := 40; -- remove atomic/exclusive access
|
constant ctrl_bus_lock_c : natural := 42; -- make atomic/exclusive access lock
|
constant ctrl_bus_ch_lock_c : natural := 41; -- evaluate atomic/exclusive lock (SC operation)
|
constant ctrl_bus_de_lock_c : natural := 43; -- remove atomic/exclusive access
|
-- alu co-processors --
|
constant ctrl_bus_ch_lock_c : natural := 44; -- evaluate atomic/exclusive lock (SC operation)
|
constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb [ALIAS]
|
-- co-processors --
|
constant ctrl_cp_trig0_c : natural := 42; -- trigger CP0
|
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select ID lsb
|
constant ctrl_cp_trig1_c : natural := 43; -- trigger CP1
|
constant ctrl_cp_id_hsb_c : natural := 46; -- cp select ID "half" significant bit
|
constant ctrl_cp_trig2_c : natural := 44; -- trigger CP2
|
constant ctrl_cp_id_msb_c : natural := 47; -- cp select ID msb
|
constant ctrl_cp_trig3_c : natural := 45; -- trigger CP3
|
-- instruction's control blocks (used by cpu co-processors) --
|
constant ctrl_cp_trig4_c : natural := 46; -- trigger CP4
|
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0
|
constant ctrl_cp_trig5_c : natural := 47; -- trigger CP5
|
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1
|
constant ctrl_cp_trig6_c : natural := 48; -- trigger CP6
|
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2
|
constant ctrl_cp_trig7_c : natural := 49; -- trigger CP7
|
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0
|
constant ctrl_cp_id_msb_c : natural := 49; -- cp select ID msb [ALIAS]
|
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1
|
-- instruction word control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2
|
constant ctrl_ir_funct3_0_c : natural := 50; -- funct3 bit 0
|
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3
|
constant ctrl_ir_funct3_1_c : natural := 51; -- funct3 bit 1
|
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4
|
constant ctrl_ir_funct3_2_c : natural := 52; -- funct3 bit 2
|
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5
|
constant ctrl_ir_funct12_0_c : natural := 53; -- funct12 bit 0
|
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6
|
constant ctrl_ir_funct12_1_c : natural := 54; -- funct12 bit 1
|
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7
|
constant ctrl_ir_funct12_2_c : natural := 55; -- funct12 bit 2
|
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8
|
constant ctrl_ir_funct12_3_c : natural := 56; -- funct12 bit 3
|
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9
|
constant ctrl_ir_funct12_4_c : natural := 57; -- funct12 bit 4
|
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10
|
constant ctrl_ir_funct12_5_c : natural := 58; -- funct12 bit 5
|
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11
|
constant ctrl_ir_funct12_6_c : natural := 59; -- funct12 bit 6
|
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0
|
constant ctrl_ir_funct12_7_c : natural := 60; -- funct12 bit 7
|
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1
|
constant ctrl_ir_funct12_8_c : natural := 61; -- funct12 bit 8
|
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2
|
constant ctrl_ir_funct12_9_c : natural := 62; -- funct12 bit 9
|
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3
|
constant ctrl_ir_funct12_10_c : natural := 63; -- funct12 bit 10
|
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4
|
constant ctrl_ir_funct12_11_c : natural := 64; -- funct12 bit 11
|
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_0_c : natural := 65; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_1_c : natural := 66; -- opcode7 bit 1
|
-- CPU status --
|
constant ctrl_ir_opcode7_2_c : natural := 67; -- opcode7 bit 2
|
constant ctrl_priv_lvl_lsb_c : natural := 70; -- privilege level lsb
|
constant ctrl_ir_opcode7_3_c : natural := 68; -- opcode7 bit 3
|
constant ctrl_priv_lvl_msb_c : natural := 71; -- privilege level msb
|
constant ctrl_ir_opcode7_4_c : natural := 69; -- opcode7 bit 4
|
constant ctrl_sleep_c : natural := 72; -- set when CPU is in sleep mode
|
constant ctrl_ir_opcode7_5_c : natural := 70; -- opcode7 bit 5
|
constant ctrl_trap_c : natural := 73; -- set when CPU is entering trap execution
|
constant ctrl_ir_opcode7_6_c : natural := 71; -- opcode7 bit 6
|
constant ctrl_debug_running_c : natural := 74; -- CPU is in debug mode when set
|
-- cpu status --
|
|
constant ctrl_priv_mode_c : natural := 72; -- effective privilege mode
|
|
constant ctrl_sleep_c : natural := 73; -- set when CPU is in sleep mode
|
|
constant ctrl_trap_c : natural := 74; -- set when CPU is entering trap execution
|
|
constant ctrl_debug_running_c : natural := 75; -- set when CPU is in debug mode
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 75; -- control bus size
|
constant ctrl_width_c : natural := 76; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 494... |
Line 497... |
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- csr read & clear bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- csr read & clear bit
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- csr r/w immediate
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- csr r/w immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- csr read & set bit immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- csr read & set bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- csr read & clear bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- csr read & clear bit immediate
|
-- fence --
|
-- fence --
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
|
|
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
| Line 608... |
Line 611... |
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
-- physical memory protection - configuration --
|
-- physical memory protection - configuration --
|
constant csr_class_pmpcfg_c : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration
|
constant csr_class_pmpcfg_c : std_ulogic_vector(09 downto 0) := x"3a" & "00"; -- pmp configuration
|
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0";
|
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0";
|
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1";
|
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1";
|
constant csr_pmpcfg2_c : std_ulogic_vector(11 downto 0) := x"3a2";
|
constant csr_pmpcfg2_c : std_ulogic_vector(11 downto 0) := x"3a2";
|
constant csr_pmpcfg3_c : std_ulogic_vector(11 downto 0) := x"3a3";
|
constant csr_pmpcfg3_c : std_ulogic_vector(11 downto 0) := x"3a3";
|
constant csr_pmpcfg4_c : std_ulogic_vector(11 downto 0) := x"3a4";
|
|
constant csr_pmpcfg5_c : std_ulogic_vector(11 downto 0) := x"3a5";
|
|
constant csr_pmpcfg6_c : std_ulogic_vector(11 downto 0) := x"3a6";
|
|
constant csr_pmpcfg7_c : std_ulogic_vector(11 downto 0) := x"3a7";
|
|
constant csr_pmpcfg8_c : std_ulogic_vector(11 downto 0) := x"3a8";
|
|
constant csr_pmpcfg9_c : std_ulogic_vector(11 downto 0) := x"3a9";
|
|
constant csr_pmpcfg10_c : std_ulogic_vector(11 downto 0) := x"3aa";
|
|
constant csr_pmpcfg11_c : std_ulogic_vector(11 downto 0) := x"3ab";
|
|
constant csr_pmpcfg12_c : std_ulogic_vector(11 downto 0) := x"3ac";
|
|
constant csr_pmpcfg13_c : std_ulogic_vector(11 downto 0) := x"3ad";
|
|
constant csr_pmpcfg14_c : std_ulogic_vector(11 downto 0) := x"3ae";
|
|
constant csr_pmpcfg15_c : std_ulogic_vector(11 downto 0) := x"3af";
|
|
-- physical memory protection - address --
|
-- physical memory protection - address --
|
|
constant csr_class_pmpaddr_c : std_ulogic_vector(07 downto 0) := x"3b"; -- pmp address
|
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0";
|
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0";
|
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1";
|
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1";
|
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2";
|
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2";
|
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3";
|
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3";
|
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4";
|
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4";
|
| Line 642... |
Line 634... |
constant csr_pmpaddr11_c : std_ulogic_vector(11 downto 0) := x"3bb";
|
constant csr_pmpaddr11_c : std_ulogic_vector(11 downto 0) := x"3bb";
|
constant csr_pmpaddr12_c : std_ulogic_vector(11 downto 0) := x"3bc";
|
constant csr_pmpaddr12_c : std_ulogic_vector(11 downto 0) := x"3bc";
|
constant csr_pmpaddr13_c : std_ulogic_vector(11 downto 0) := x"3bd";
|
constant csr_pmpaddr13_c : std_ulogic_vector(11 downto 0) := x"3bd";
|
constant csr_pmpaddr14_c : std_ulogic_vector(11 downto 0) := x"3be";
|
constant csr_pmpaddr14_c : std_ulogic_vector(11 downto 0) := x"3be";
|
constant csr_pmpaddr15_c : std_ulogic_vector(11 downto 0) := x"3bf";
|
constant csr_pmpaddr15_c : std_ulogic_vector(11 downto 0) := x"3bf";
|
constant csr_pmpaddr16_c : std_ulogic_vector(11 downto 0) := x"3c0";
|
|
constant csr_pmpaddr17_c : std_ulogic_vector(11 downto 0) := x"3c1";
|
|
constant csr_pmpaddr18_c : std_ulogic_vector(11 downto 0) := x"3c2";
|
|
constant csr_pmpaddr19_c : std_ulogic_vector(11 downto 0) := x"3c3";
|
|
constant csr_pmpaddr20_c : std_ulogic_vector(11 downto 0) := x"3c4";
|
|
constant csr_pmpaddr21_c : std_ulogic_vector(11 downto 0) := x"3c5";
|
|
constant csr_pmpaddr22_c : std_ulogic_vector(11 downto 0) := x"3c6";
|
|
constant csr_pmpaddr23_c : std_ulogic_vector(11 downto 0) := x"3c7";
|
|
constant csr_pmpaddr24_c : std_ulogic_vector(11 downto 0) := x"3c8";
|
|
constant csr_pmpaddr25_c : std_ulogic_vector(11 downto 0) := x"3c9";
|
|
constant csr_pmpaddr26_c : std_ulogic_vector(11 downto 0) := x"3ca";
|
|
constant csr_pmpaddr27_c : std_ulogic_vector(11 downto 0) := x"3cb";
|
|
constant csr_pmpaddr28_c : std_ulogic_vector(11 downto 0) := x"3cc";
|
|
constant csr_pmpaddr29_c : std_ulogic_vector(11 downto 0) := x"3cd";
|
|
constant csr_pmpaddr30_c : std_ulogic_vector(11 downto 0) := x"3ce";
|
|
constant csr_pmpaddr31_c : std_ulogic_vector(11 downto 0) := x"3cf";
|
|
constant csr_pmpaddr32_c : std_ulogic_vector(11 downto 0) := x"3d0";
|
|
constant csr_pmpaddr33_c : std_ulogic_vector(11 downto 0) := x"3d1";
|
|
constant csr_pmpaddr34_c : std_ulogic_vector(11 downto 0) := x"3d2";
|
|
constant csr_pmpaddr35_c : std_ulogic_vector(11 downto 0) := x"3d3";
|
|
constant csr_pmpaddr36_c : std_ulogic_vector(11 downto 0) := x"3d4";
|
|
constant csr_pmpaddr37_c : std_ulogic_vector(11 downto 0) := x"3d5";
|
|
constant csr_pmpaddr38_c : std_ulogic_vector(11 downto 0) := x"3d6";
|
|
constant csr_pmpaddr39_c : std_ulogic_vector(11 downto 0) := x"3d7";
|
|
constant csr_pmpaddr40_c : std_ulogic_vector(11 downto 0) := x"3d8";
|
|
constant csr_pmpaddr41_c : std_ulogic_vector(11 downto 0) := x"3d9";
|
|
constant csr_pmpaddr42_c : std_ulogic_vector(11 downto 0) := x"3da";
|
|
constant csr_pmpaddr43_c : std_ulogic_vector(11 downto 0) := x"3db";
|
|
constant csr_pmpaddr44_c : std_ulogic_vector(11 downto 0) := x"3dc";
|
|
constant csr_pmpaddr45_c : std_ulogic_vector(11 downto 0) := x"3dd";
|
|
constant csr_pmpaddr46_c : std_ulogic_vector(11 downto 0) := x"3de";
|
|
constant csr_pmpaddr47_c : std_ulogic_vector(11 downto 0) := x"3df";
|
|
constant csr_pmpaddr48_c : std_ulogic_vector(11 downto 0) := x"3e0";
|
|
constant csr_pmpaddr49_c : std_ulogic_vector(11 downto 0) := x"3e1";
|
|
constant csr_pmpaddr50_c : std_ulogic_vector(11 downto 0) := x"3e2";
|
|
constant csr_pmpaddr51_c : std_ulogic_vector(11 downto 0) := x"3e3";
|
|
constant csr_pmpaddr52_c : std_ulogic_vector(11 downto 0) := x"3e4";
|
|
constant csr_pmpaddr53_c : std_ulogic_vector(11 downto 0) := x"3e5";
|
|
constant csr_pmpaddr54_c : std_ulogic_vector(11 downto 0) := x"3e6";
|
|
constant csr_pmpaddr55_c : std_ulogic_vector(11 downto 0) := x"3e7";
|
|
constant csr_pmpaddr56_c : std_ulogic_vector(11 downto 0) := x"3e8";
|
|
constant csr_pmpaddr57_c : std_ulogic_vector(11 downto 0) := x"3e9";
|
|
constant csr_pmpaddr58_c : std_ulogic_vector(11 downto 0) := x"3ea";
|
|
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
|
|
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
|
|
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
|
|
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
|
|
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
|
|
-- trigger module registers --
|
-- trigger module registers --
|
constant csr_class_trigger_c : std_ulogic_vector(07 downto 0) := x"7a"; -- trigger registers
|
constant csr_class_trigger_c : std_ulogic_vector(07 downto 0) := x"7a"; -- trigger registers
|
constant csr_tselect_c : std_ulogic_vector(11 downto 0) := x"7a0";
|
constant csr_tselect_c : std_ulogic_vector(11 downto 0) := x"7a0";
|
constant csr_tdata1_c : std_ulogic_vector(11 downto 0) := x"7a1";
|
constant csr_tdata1_c : std_ulogic_vector(11 downto 0) := x"7a1";
|
constant csr_tdata2_c : std_ulogic_vector(11 downto 0) := x"7a2";
|
constant csr_tdata2_c : std_ulogic_vector(11 downto 0) := x"7a2";
|
| Line 777... |
Line 721... |
-- <<< standard read-only CSRs >>> --
|
-- <<< standard read-only CSRs >>> --
|
-- user counters/timers --
|
-- user counters/timers --
|
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00";
|
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00";
|
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01";
|
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01";
|
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02";
|
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02";
|
|
--
|
|
constant csr_hpmcounter3_c : std_ulogic_vector(11 downto 0) := x"c03";
|
|
constant csr_hpmcounter4_c : std_ulogic_vector(11 downto 0) := x"c04";
|
|
constant csr_hpmcounter5_c : std_ulogic_vector(11 downto 0) := x"c05";
|
|
constant csr_hpmcounter6_c : std_ulogic_vector(11 downto 0) := x"c06";
|
|
constant csr_hpmcounter7_c : std_ulogic_vector(11 downto 0) := x"c07";
|
|
constant csr_hpmcounter8_c : std_ulogic_vector(11 downto 0) := x"c08";
|
|
constant csr_hpmcounter9_c : std_ulogic_vector(11 downto 0) := x"c09";
|
|
constant csr_hpmcounter10_c : std_ulogic_vector(11 downto 0) := x"c0a";
|
|
constant csr_hpmcounter11_c : std_ulogic_vector(11 downto 0) := x"c0b";
|
|
constant csr_hpmcounter12_c : std_ulogic_vector(11 downto 0) := x"c0c";
|
|
constant csr_hpmcounter13_c : std_ulogic_vector(11 downto 0) := x"c0d";
|
|
constant csr_hpmcounter14_c : std_ulogic_vector(11 downto 0) := x"c0e";
|
|
constant csr_hpmcounter15_c : std_ulogic_vector(11 downto 0) := x"c0f";
|
|
constant csr_hpmcounter16_c : std_ulogic_vector(11 downto 0) := x"c10";
|
|
constant csr_hpmcounter17_c : std_ulogic_vector(11 downto 0) := x"c11";
|
|
constant csr_hpmcounter18_c : std_ulogic_vector(11 downto 0) := x"c12";
|
|
constant csr_hpmcounter19_c : std_ulogic_vector(11 downto 0) := x"c13";
|
|
constant csr_hpmcounter20_c : std_ulogic_vector(11 downto 0) := x"c14";
|
|
constant csr_hpmcounter21_c : std_ulogic_vector(11 downto 0) := x"c15";
|
|
constant csr_hpmcounter22_c : std_ulogic_vector(11 downto 0) := x"c16";
|
|
constant csr_hpmcounter23_c : std_ulogic_vector(11 downto 0) := x"c17";
|
|
constant csr_hpmcounter24_c : std_ulogic_vector(11 downto 0) := x"c18";
|
|
constant csr_hpmcounter25_c : std_ulogic_vector(11 downto 0) := x"c19";
|
|
constant csr_hpmcounter26_c : std_ulogic_vector(11 downto 0) := x"c1a";
|
|
constant csr_hpmcounter27_c : std_ulogic_vector(11 downto 0) := x"c1b";
|
|
constant csr_hpmcounter28_c : std_ulogic_vector(11 downto 0) := x"c1c";
|
|
constant csr_hpmcounter29_c : std_ulogic_vector(11 downto 0) := x"c1d";
|
|
constant csr_hpmcounter30_c : std_ulogic_vector(11 downto 0) := x"c1e";
|
|
constant csr_hpmcounter31_c : std_ulogic_vector(11 downto 0) := x"c1f";
|
|
--
|
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80";
|
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80";
|
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81";
|
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81";
|
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82";
|
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82";
|
|
--
|
|
constant csr_hpmcounter3h_c : std_ulogic_vector(11 downto 0) := x"c83";
|
|
constant csr_hpmcounter4h_c : std_ulogic_vector(11 downto 0) := x"c84";
|
|
constant csr_hpmcounter5h_c : std_ulogic_vector(11 downto 0) := x"c85";
|
|
constant csr_hpmcounter6h_c : std_ulogic_vector(11 downto 0) := x"c86";
|
|
constant csr_hpmcounter7h_c : std_ulogic_vector(11 downto 0) := x"c87";
|
|
constant csr_hpmcounter8h_c : std_ulogic_vector(11 downto 0) := x"c88";
|
|
constant csr_hpmcounter9h_c : std_ulogic_vector(11 downto 0) := x"c89";
|
|
constant csr_hpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"c8a";
|
|
constant csr_hpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"c8b";
|
|
constant csr_hpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"c8c";
|
|
constant csr_hpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"c8d";
|
|
constant csr_hpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"c8e";
|
|
constant csr_hpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"c8f";
|
|
constant csr_hpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"c90";
|
|
constant csr_hpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"c91";
|
|
constant csr_hpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"c92";
|
|
constant csr_hpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"c93";
|
|
constant csr_hpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"c94";
|
|
constant csr_hpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"c95";
|
|
constant csr_hpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"c96";
|
|
constant csr_hpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"c97";
|
|
constant csr_hpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"c98";
|
|
constant csr_hpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"c99";
|
|
constant csr_hpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"c9a";
|
|
constant csr_hpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"c9b";
|
|
constant csr_hpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"c9c";
|
|
constant csr_hpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"c9d";
|
|
constant csr_hpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"c9e";
|
|
constant csr_hpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"c9f";
|
-- machine information registers --
|
-- machine information registers --
|
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11";
|
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11";
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
|
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
|
|
|
-- <<< NEORV32-specific (custom) read-only CSRs >>> ---
|
-- <<< NEORV32-specific (custom) read-only CSRs >>> ---
|
-- machine extended ISA extensionss information --
|
-- machine extended ISA extensions information --
|
constant csr_mxisa_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
constant csr_mxisa_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
|
|
-- CPU Co-Processor IDs -------------------------------------------------------------------
|
-- CPU Co-Processor IDs (one-hot!) --------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA)
|
constant cp_sel_shifter_c : std_ulogic_vector(7 downto 0) := "00000001"; -- CP0: shift operations (base ISA)
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions)
|
constant cp_sel_muldiv_c : std_ulogic_vector(7 downto 0) := "00000010"; -- CP1: multiplication/division operations ('M' extensions)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(7 downto 0) := "00000100"; -- CP2: bit manipulation ('B' extensions)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(7 downto 0) := "00001000"; -- CP3: floating-point unit ('Zfinx' extension)
|
constant cp_sel_cfu_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: custom instructions CFU ('Zxcfu' extension)
|
constant cp_sel_cfu_c : std_ulogic_vector(7 downto 0) := "00010000"; -- CP4: custom instructions CFU ('Zxcfu' extension)
|
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved
|
--constant cp_sel_res5_c : std_ulogic_vector(7 downto 0) := "00100000"; -- CP5: reserved
|
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved
|
--constant cp_sel_res6_c : std_ulogic_vector(7 downto 0) := "01000000"; -- CP6: reserved
|
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved
|
--constant cp_sel_res7_c : std_ulogic_vector(7 downto 0) := "10000000"; -- CP7: reserved
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes [DO NOT CHANGE ENCODING!] -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- ALU core [DO NOT CHANGE ENCODING!] --
|
constant alu_op_add_c : std_ulogic_vector(2 downto 0) := "000"; -- result <= A + B
|
constant alu_op_add_c : std_ulogic_vector(2 downto 0) := "000"; -- alu_result <= A + B
|
constant alu_op_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- result <= A - B
|
constant alu_op_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- alu_result <= A - B
|
constant alu_op_cp_c : std_ulogic_vector(2 downto 0) := "010"; -- result <= co-processor
|
--constant alu_op_mova_c : std_ulogic_vector(2 downto 0) := "010"; -- alu_result <= A (rs1)
|
constant alu_op_slt_c : std_ulogic_vector(2 downto 0) := "011"; -- result <= A < B
|
constant alu_op_slt_c : std_ulogic_vector(2 downto 0) := "011"; -- alu_result <= A < B
|
constant alu_op_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- result <= B
|
constant alu_op_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- alu_result <= B
|
constant alu_op_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- result <= A xor B
|
constant alu_op_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- alu_result <= A xor B
|
constant alu_op_or_c : std_ulogic_vector(2 downto 0) := "110"; -- result <= A or B
|
constant alu_op_or_c : std_ulogic_vector(2 downto 0) := "110"; -- alu_result <= A or B
|
constant alu_op_and_c : std_ulogic_vector(2 downto 0) := "111"; -- result <= A and B
|
constant alu_op_and_c : std_ulogic_vector(2 downto 0) := "111"; -- alu_result <= A and B
|
|
-- function select (actual ALU result) --
|
-- Register File Input Select -------------------------------------------------------------
|
constant alu_func_core_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= alu_result
|
-- -------------------------------------------------------------------------------------------
|
constant alu_func_nxpc_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= next_PC
|
constant rf_mux_alu_c : std_ulogic_vector(1 downto 0) := "00"; -- register file <= alu result
|
constant alu_func_csrr_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= CSR read
|
constant rf_mux_mem_c : std_ulogic_vector(1 downto 0) := "01"; -- register file <= memory read data
|
constant alu_func_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle)
|
constant rf_mux_csr_c : std_ulogic_vector(1 downto 0) := "10"; -- register file <= CSR read data
|
|
constant rf_mux_npc_c : std_ulogic_vector(1 downto 0) := "11"; -- register file <= next-PC (for branch-and-link)
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
| Line 872... |
Line 878... |
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async)
|
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async)
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instruction access fault
|
constant exc_iaccess_c : natural := 0; -- instruction access fault
|
constant exception_iillegal_c : natural := 1; -- illegal instruction
|
constant exc_iillegal_c : natural := 1; -- illegal instruction
|
constant exception_ialign_c : natural := 2; -- instruction address misaligned
|
constant exc_ialign_c : natural := 2; -- instruction address misaligned
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exc_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode
|
constant exc_u_envcall_c : natural := 4; -- ENV call from u-mode
|
constant exception_break_c : natural := 5; -- breakpoint
|
constant exc_break_c : natural := 5; -- breakpoint
|
constant exception_salign_c : natural := 6; -- store address misaligned
|
constant exc_salign_c : natural := 6; -- store address misaligned
|
constant exception_lalign_c : natural := 7; -- load address misaligned
|
constant exc_lalign_c : natural := 7; -- load address misaligned
|
constant exception_saccess_c : natural := 8; -- store access fault
|
constant exc_saccess_c : natural := 8; -- store access fault
|
constant exception_laccess_c : natural := 9; -- load access fault
|
constant exc_laccess_c : natural := 9; -- load access fault
|
-- for debug mode only --
|
-- for debug mode only --
|
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
|
constant exc_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
|
constant exception_db_hw_c : natural := 11; -- enter debug mode via hw trigger ("sync EXCEPTION")
|
constant exc_db_hw_c : natural := 11; -- enter debug mode via hw trigger ("sync EXCEPTION")
|
--
|
--
|
constant exception_width_c : natural := 12; -- length of this list in bits
|
constant exc_width_c : natural := 12; -- length of this list in bits
|
-- interrupt source bits --
|
-- interrupt source bits --
|
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
constant irq_msw_irq_c : natural := 0; -- machine software interrupt
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant irq_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant irq_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
constant irq_firq_0_c : natural := 3; -- fast interrupt channel 0
|
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
|
constant irq_firq_1_c : natural := 4; -- fast interrupt channel 1
|
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
|
constant irq_firq_2_c : natural := 5; -- fast interrupt channel 2
|
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
|
constant irq_firq_3_c : natural := 6; -- fast interrupt channel 3
|
constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4
|
constant irq_firq_4_c : natural := 7; -- fast interrupt channel 4
|
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5
|
constant irq_firq_5_c : natural := 8; -- fast interrupt channel 5
|
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6
|
constant irq_firq_6_c : natural := 9; -- fast interrupt channel 6
|
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7
|
constant irq_firq_7_c : natural := 10; -- fast interrupt channel 7
|
constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8
|
constant irq_firq_8_c : natural := 11; -- fast interrupt channel 8
|
constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9
|
constant irq_firq_9_c : natural := 12; -- fast interrupt channel 9
|
constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10
|
constant irq_firq_10_c : natural := 13; -- fast interrupt channel 10
|
constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11
|
constant irq_firq_11_c : natural := 14; -- fast interrupt channel 11
|
constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12
|
constant irq_firq_12_c : natural := 15; -- fast interrupt channel 12
|
constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13
|
constant irq_firq_13_c : natural := 16; -- fast interrupt channel 13
|
constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14
|
constant irq_firq_14_c : natural := 17; -- fast interrupt channel 14
|
constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15
|
constant irq_firq_15_c : natural := 18; -- fast interrupt channel 15
|
-- for debug mode only --
|
-- for debug mode only --
|
constant interrupt_db_halt_c : natural := 19; -- enter debug mode via external halt request ("async IRQ")
|
constant irq_db_halt_c : natural := 19; -- enter debug mode via external halt request ("async IRQ")
|
constant interrupt_db_step_c : natural := 20; -- enter debug mode via single-stepping ("async IRQ")
|
constant irq_db_step_c : natural := 20; -- enter debug mode via single-stepping ("async IRQ")
|
--
|
--
|
constant interrupt_width_c : natural := 21; -- length of this list in bits
|
constant irq_width_c : natural := 21; -- length of this list in bits
|
|
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_m_c : std_ulogic := '1'; -- machine mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
constant priv_mode_u_c : std_ulogic := '0'; -- user mode
|
|
|
-- HPM Event System -----------------------------------------------------------------------
|
-- HPM Event System -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant hpmcnt_event_cy_c : natural := 0; -- Active cycle
|
constant hpmcnt_event_cy_c : natural := 0; -- Active cycle
|
constant hpmcnt_event_never_c : natural := 1; -- Unused / never (actually, this would be used for TIME)
|
constant hpmcnt_event_never_c : natural := 1; -- Unused / never (actually, this would be used for TIME)
|
| Line 979... |
Line 985... |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
|
-- Internal Instruction memory (IMEM) --
|
-- Internal Instruction memory (IMEM) --
|
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
|
| Line 1140... |
Line 1146... |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..16)
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
);
|
);
|
port (
|
port (
|
| Line 1163... |
Line 1169... |
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic; -- privilege level
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1175... |
Line 1181... |
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic; -- privilege level
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
| Line 1218... |
Line 1224... |
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..16)
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
|
);
|
);
|
port (
|
port (
|
| Line 1282... |
Line 1288... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC
|
-- data output --
|
-- data output --
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
);
|
);
|
end component;
|
end component;
|
| Line 1313... |
Line 1321... |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC
|
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
|
-- data output --
|
-- data output --
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
|
fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
|
| Line 1437... |
Line 1443... |
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..16)
|
PMP_MIN_GRANULARITY : natural -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 1531... |
Line 1537... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
clear_i : in std_ulogic; -- cache clear
|
clear_i : in std_ulogic; -- cache clear
|
|
miss_o : out std_ulogic; -- cache miss
|
-- host controller interface --
|
-- host controller interface --
|
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1600... |
Line 1607... |
end component;
|
end component;
|
|
|
-- Component: CPU Compressed Instructions De-Compressor -----------------------------------
|
-- Component: CPU Compressed Instructions De-Compressor -----------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_decompressor
|
component neorv32_cpu_decompressor
|
|
generic (
|
|
FPU_ENABLE : boolean -- floating-point instruction enabled
|
|
);
|
port (
|
port (
|
-- instruction input --
|
-- instruction input --
|
ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
|
ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
|
-- instruction output --
|
-- instruction output --
|
ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
|
ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
|
| Line 1881... |
Line 1891... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
lock_i : in std_ulogic; -- exclusive access request
|
lock_i : in std_ulogic; -- exclusive access request
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
tmo_o : out std_ulogic; -- transfer timeout
|
tmo_o : out std_ulogic; -- transfer timeout
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic; -- current CPU privilege level
|
ext_o : out std_ulogic; -- active external access
|
ext_o : out std_ulogic; -- active external access
|
-- xip configuration --
|
-- xip configuration --
|
xip_en_i : in std_ulogic; -- XIP module enabled
|
xip_en_i : in std_ulogic; -- XIP module enabled
|
xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
|
xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
|
-- wishbone interface --
|
-- wishbone interface --
|
| Line 2074... |
Line 2084... |
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..16)
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
|
