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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_spi.vhd] - Diff between revs 6 and 22
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| Rev 6 |
Rev 22 |
| Line 47... |
Line 47... |
-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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| Line 138... |
Line 137... |
spi_start <= '0';
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spi_start <= '0';
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-- write access --
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-- write access --
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if (wren = '1') then
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if (wren = '1') then
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-- control regsiter --
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-- control regsiter --
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if (addr = spi_ctrl_addr_c) then
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if (addr = spi_ctrl_addr_c) then
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if (ben_i(0) = '1') then
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ctrl <= data_i(ctrl'left downto 0);
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ctrl(07 downto 00) <= data_i(07 downto 00);
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end if;
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if (ben_i(1) = '1') then
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ctrl(15 downto 08) <= data_i(15 downto 08);
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end if;
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if (ben_i(2) = '1') then
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ctrl(16 downto 16) <= data_i(16 downto 16);
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end if;
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end if;
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end if;
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-- data regsiter --
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-- data regsiter --
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if (addr = spi_rtx_addr_c) then
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if (addr = spi_rtx_addr_c) then
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tx_data <= data_i;
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spi_start <= '1';
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spi_start <= '1';
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for i in 0 to 3 loop
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if (ben_i(i) = '1') then
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tx_data(7+i*8 downto 0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end loop; -- i
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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