URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_spi.vhd] - Diff between revs 6 and 22
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 6 |
Rev 22 |
| Line 47... |
Line 47... |
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
| Line 138... |
Line 137... |
spi_start <= '0';
|
spi_start <= '0';
|
-- write access --
|
-- write access --
|
if (wren = '1') then
|
if (wren = '1') then
|
-- control regsiter --
|
-- control regsiter --
|
if (addr = spi_ctrl_addr_c) then
|
if (addr = spi_ctrl_addr_c) then
|
if (ben_i(0) = '1') then
|
ctrl <= data_i(ctrl'left downto 0);
|
ctrl(07 downto 00) <= data_i(07 downto 00);
|
|
end if;
|
|
if (ben_i(1) = '1') then
|
|
ctrl(15 downto 08) <= data_i(15 downto 08);
|
|
end if;
|
|
if (ben_i(2) = '1') then
|
|
ctrl(16 downto 16) <= data_i(16 downto 16);
|
|
end if;
|
|
end if;
|
end if;
|
-- data regsiter --
|
-- data regsiter --
|
if (addr = spi_rtx_addr_c) then
|
if (addr = spi_rtx_addr_c) then
|
|
tx_data <= data_i;
|
spi_start <= '1';
|
spi_start <= '1';
|
for i in 0 to 3 loop
|
|
if (ben_i(i) = '1') then
|
|
tx_data(7+i*8 downto 0+i*8) <= data_i(7+i*8 downto 0+i*8);
|
|
end if;
|
|
end loop; -- i
|
|
end if;
|
end if;
|
end if;
|
end if;
|
-- read access --
|
-- read access --
|
data_o <= (others => '0');
|
data_o <= (others => '0');
|
if (rden = '1') then
|
if (rden = '1') then
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.