| Line 71... |
Line 71... |
-- IO space: module base address --
|
-- IO space: module base address --
|
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
|
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
|
constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit
|
constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit
|
|
|
-- control register --
|
-- control register --
|
constant ctrl_spi_cs0_c : natural := 0; -- r/w: spi CS 0
|
constant ctrl_cs0_c : natural := 0; -- r/w: spi CS 0
|
constant ctrl_spi_cs1_c : natural := 1; -- r/w: spi CS 1
|
constant ctrl_cs1_c : natural := 1; -- r/w: spi CS 1
|
constant ctrl_spi_cs2_c : natural := 2; -- r/w: spi CS 2
|
constant ctrl_cs2_c : natural := 2; -- r/w: spi CS 2
|
constant ctrl_spi_cs3_c : natural := 3; -- r/w: spi CS 3
|
constant ctrl_cs3_c : natural := 3; -- r/w: spi CS 3
|
constant ctrl_spi_cs4_c : natural := 4; -- r/w: spi CS 4
|
constant ctrl_cs4_c : natural := 4; -- r/w: spi CS 4
|
constant ctrl_spi_cs5_c : natural := 5; -- r/w: spi CS 5
|
constant ctrl_cs5_c : natural := 5; -- r/w: spi CS 5
|
constant ctrl_spi_cs6_c : natural := 6; -- r/w: spi CS 6
|
constant ctrl_cs6_c : natural := 6; -- r/w: spi CS 6
|
constant ctrl_spi_cs7_c : natural := 7; -- r/w: spi CS 7
|
constant ctrl_cs7_c : natural := 7; -- r/w: spi CS 7
|
--
|
--
|
constant ctrl_spi_en_c : natural := 8; -- r/w: spi enable
|
constant ctrl_en_c : natural := 8; -- r/w: spi enable
|
constant ctrl_spi_cpha_c : natural := 9; -- r/w: spi clock phase
|
constant ctrl_cpha_c : natural := 9; -- r/w: spi clock phase
|
constant ctrl_spi_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0
|
constant ctrl_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0
|
constant ctrl_spi_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1
|
constant ctrl_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1
|
constant ctrl_spi_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2
|
constant ctrl_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2
|
constant ctrl_spi_size0_c : natural := 13; -- r/w: data size (00: 8-bit, 01: 16-bit)
|
constant ctrl_size0_c : natural := 13; -- r/w: data size lsb (00: 8-bit, 01: 16-bit)
|
constant ctrl_spi_size1_c : natural := 14; -- r/w: data size (10: 24-bit, 11: 32-bit)
|
constant ctrl_size1_c : natural := 14; -- r/w: data size msb (10: 24-bit, 11: 32-bit)
|
constant ctrl_spi_cpol_c : natural := 15; -- r/w: spi clock polarity
|
constant ctrl_cpol_c : natural := 15; -- r/w: spi clock polarity
|
--
|
--
|
constant ctrl_spi_busy_c : natural := 31; -- r/-: spi transceiver is busy
|
constant ctrl_busy_c : natural := 31; -- r/-: spi transceiver is busy
|
--
|
--
|
signal ctrl : std_ulogic_vector(15 downto 0);
|
signal ctrl : std_ulogic_vector(15 downto 0);
|
|
|
-- access control --
|
-- access control --
|
signal acc_en : std_ulogic; -- module access enable
|
signal acc_en : std_ulogic; -- module access enable
|
| Line 104... |
Line 104... |
-- clock generator --
|
-- clock generator --
|
signal spi_clk_en : std_ulogic;
|
signal spi_clk_en : std_ulogic;
|
|
|
-- spi transceiver --
|
-- spi transceiver --
|
type rtx_engine_t is record
|
type rtx_engine_t is record
|
|
state : std_ulogic_vector(02 downto 0);
|
busy : std_ulogic;
|
busy : std_ulogic;
|
state0 : std_ulogic;
|
start : std_ulogic;
|
state1 : std_ulogic;
|
sreg : std_ulogic_vector(31 downto 0);
|
rtx_sreg : std_ulogic_vector(31 downto 0);
|
|
bitcnt : std_ulogic_vector(05 downto 0);
|
bitcnt : std_ulogic_vector(05 downto 0);
|
bytecnt : std_ulogic_vector(02 downto 0);
|
bytecnt : std_ulogic_vector(02 downto 0);
|
sdi_ff0 : std_ulogic;
|
sdi_sync : std_ulogic_vector(01 downto 0);
|
sdi_ff1 : std_ulogic;
|
|
end record;
|
end record;
|
signal rtx_engine : rtx_engine_t;
|
signal rtx_engine : rtx_engine_t;
|
|
|
begin
|
begin
|
|
|
| Line 136... |
Line 135... |
ack_o <= rden or wren;
|
ack_o <= rden or wren;
|
|
|
-- write access --
|
-- write access --
|
if (wren = '1') then
|
if (wren = '1') then
|
if (addr = spi_ctrl_addr_c) then -- control register
|
if (addr = spi_ctrl_addr_c) then -- control register
|
ctrl(ctrl_spi_cs0_c) <= data_i(ctrl_spi_cs0_c);
|
ctrl(ctrl_cs0_c) <= data_i(ctrl_cs0_c);
|
ctrl(ctrl_spi_cs1_c) <= data_i(ctrl_spi_cs1_c);
|
ctrl(ctrl_cs1_c) <= data_i(ctrl_cs1_c);
|
ctrl(ctrl_spi_cs2_c) <= data_i(ctrl_spi_cs2_c);
|
ctrl(ctrl_cs2_c) <= data_i(ctrl_cs2_c);
|
ctrl(ctrl_spi_cs3_c) <= data_i(ctrl_spi_cs3_c);
|
ctrl(ctrl_cs3_c) <= data_i(ctrl_cs3_c);
|
ctrl(ctrl_spi_cs4_c) <= data_i(ctrl_spi_cs4_c);
|
ctrl(ctrl_cs4_c) <= data_i(ctrl_cs4_c);
|
ctrl(ctrl_spi_cs5_c) <= data_i(ctrl_spi_cs5_c);
|
ctrl(ctrl_cs5_c) <= data_i(ctrl_cs5_c);
|
ctrl(ctrl_spi_cs6_c) <= data_i(ctrl_spi_cs6_c);
|
ctrl(ctrl_cs6_c) <= data_i(ctrl_cs6_c);
|
ctrl(ctrl_spi_cs7_c) <= data_i(ctrl_spi_cs7_c);
|
ctrl(ctrl_cs7_c) <= data_i(ctrl_cs7_c);
|
--
|
--
|
ctrl(ctrl_spi_en_c) <= data_i(ctrl_spi_en_c);
|
ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
|
ctrl(ctrl_spi_cpha_c) <= data_i(ctrl_spi_cpha_c);
|
ctrl(ctrl_cpha_c) <= data_i(ctrl_cpha_c);
|
ctrl(ctrl_spi_prsc0_c) <= data_i(ctrl_spi_prsc0_c);
|
ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
|
ctrl(ctrl_spi_prsc1_c) <= data_i(ctrl_spi_prsc1_c);
|
ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
|
ctrl(ctrl_spi_prsc2_c) <= data_i(ctrl_spi_prsc2_c);
|
ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
|
ctrl(ctrl_spi_size0_c) <= data_i(ctrl_spi_size0_c);
|
ctrl(ctrl_size0_c) <= data_i(ctrl_size0_c);
|
ctrl(ctrl_spi_size1_c) <= data_i(ctrl_spi_size1_c);
|
ctrl(ctrl_size1_c) <= data_i(ctrl_size1_c);
|
ctrl(ctrl_spi_cpol_c) <= data_i(ctrl_spi_cpol_c);
|
ctrl(ctrl_cpol_c) <= data_i(ctrl_cpol_c);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
data_o <= (others => '0');
|
data_o <= (others => '0');
|
if (rden = '1') then
|
if (rden = '1') then
|
if (addr = spi_ctrl_addr_c) then -- control register
|
if (addr = spi_ctrl_addr_c) then -- control register
|
data_o(ctrl_spi_cs0_c) <= ctrl(ctrl_spi_cs0_c);
|
data_o(ctrl_cs0_c) <= ctrl(ctrl_cs0_c);
|
data_o(ctrl_spi_cs1_c) <= ctrl(ctrl_spi_cs1_c);
|
data_o(ctrl_cs1_c) <= ctrl(ctrl_cs1_c);
|
data_o(ctrl_spi_cs2_c) <= ctrl(ctrl_spi_cs2_c);
|
data_o(ctrl_cs2_c) <= ctrl(ctrl_cs2_c);
|
data_o(ctrl_spi_cs3_c) <= ctrl(ctrl_spi_cs3_c);
|
data_o(ctrl_cs3_c) <= ctrl(ctrl_cs3_c);
|
data_o(ctrl_spi_cs4_c) <= ctrl(ctrl_spi_cs4_c);
|
data_o(ctrl_cs4_c) <= ctrl(ctrl_cs4_c);
|
data_o(ctrl_spi_cs5_c) <= ctrl(ctrl_spi_cs5_c);
|
data_o(ctrl_cs5_c) <= ctrl(ctrl_cs5_c);
|
data_o(ctrl_spi_cs6_c) <= ctrl(ctrl_spi_cs6_c);
|
data_o(ctrl_cs6_c) <= ctrl(ctrl_cs6_c);
|
data_o(ctrl_spi_cs7_c) <= ctrl(ctrl_spi_cs7_c);
|
data_o(ctrl_cs7_c) <= ctrl(ctrl_cs7_c);
|
--
|
--
|
data_o(ctrl_spi_en_c) <= ctrl(ctrl_spi_en_c);
|
data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
|
data_o(ctrl_spi_cpha_c) <= ctrl(ctrl_spi_cpha_c);
|
data_o(ctrl_cpha_c) <= ctrl(ctrl_cpha_c);
|
data_o(ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc0_c);
|
data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
|
data_o(ctrl_spi_prsc1_c) <= ctrl(ctrl_spi_prsc1_c);
|
data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
|
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c);
|
data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
|
data_o(ctrl_spi_size0_c) <= ctrl(ctrl_spi_size0_c);
|
data_o(ctrl_size0_c) <= ctrl(ctrl_size0_c);
|
data_o(ctrl_spi_size1_c) <= ctrl(ctrl_spi_size1_c);
|
data_o(ctrl_size1_c) <= ctrl(ctrl_size1_c);
|
data_o(ctrl_spi_cpol_c) <= ctrl(ctrl_spi_cpol_c);
|
data_o(ctrl_cpol_c) <= ctrl(ctrl_cpol_c);
|
--
|
--
|
data_o(ctrl_spi_busy_c) <= rtx_engine.busy;
|
data_o(ctrl_busy_c) <= rtx_engine.busy;
|
else -- data register (spi_rtx_addr_c)
|
else -- data register (spi_rtx_addr_c)
|
data_o <= rtx_engine.rtx_sreg;
|
data_o <= rtx_engine.sreg;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process rw_access;
|
end process rw_access;
|
|
|
-- direct chip-select (CS), output is low-active --
|
-- direct chip-select (CS), output is low-active --
|
spi_csn_o(7 downto 0) <= not ctrl(ctrl_spi_cs7_c downto ctrl_spi_cs0_c);
|
spi_csn_o(7 downto 0) <= not ctrl(ctrl_cs7_c downto ctrl_cs0_c);
|
|
|
|
-- trigger new SPI transmission --
|
|
rtx_engine.start <= '1' when (wren = '1') and (addr = spi_rtx_addr_c) else '0';
|
|
|
|
|
|
-- Clock Selection ------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
clkgen_en_o <= ctrl(ctrl_en_c); -- clock generator enable
|
|
spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); -- clock select
|
|
|
|
|
-- Transmission Data Size -----------------------------------------------------------------
|
-- Transmission Data Size -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
data_size: process(ctrl)
|
data_size: process(ctrl)
|
begin
|
begin
|
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is
|
case ctrl(ctrl_size1_c downto ctrl_size0_c) is
|
when "00" => rtx_engine.bytecnt <= "001"; -- 1-byte mode
|
when "00" => rtx_engine.bytecnt <= "001"; -- 1-byte mode
|
when "01" => rtx_engine.bytecnt <= "010"; -- 2-byte mode
|
when "01" => rtx_engine.bytecnt <= "010"; -- 2-byte mode
|
when "10" => rtx_engine.bytecnt <= "011"; -- 3-byte mode
|
when "10" => rtx_engine.bytecnt <= "011"; -- 3-byte mode
|
when others => rtx_engine.bytecnt <= "100"; -- 4-byte mode
|
when others => rtx_engine.bytecnt <= "100"; -- 4-byte mode
|
end case;
|
end case;
|
end process data_size;
|
end process data_size;
|
|
|
|
|
-- Clock Selection ------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
clkgen_en_o <= ctrl(ctrl_spi_en_c); -- clock generator enable
|
|
spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c)))); -- clock select
|
|
|
|
|
|
-- SPI Transceiver ------------------------------------------------------------------------
|
-- SPI Transceiver ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
spi_rtx_unit: process(clk_i)
|
spi_rtx_unit: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- input (sdi) synchronizer --
|
-- input (sdi) synchronizer --
|
rtx_engine.sdi_ff0 <= spi_sdi_i;
|
rtx_engine.sdi_sync <= rtx_engine.sdi_sync(0) & spi_sdi_i;
|
rtx_engine.sdi_ff1 <= rtx_engine.sdi_ff0;
|
|
|
-- output (sdo) buffer --
|
|
case ctrl(ctrl_size1_c downto ctrl_size0_c) is
|
|
when "00" => spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode
|
|
when "01" => spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode
|
|
when "10" => spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode
|
|
when others => spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode
|
|
end case;
|
|
|
|
-- defaults --
|
|
spi_sck_o <= ctrl(ctrl_cpol_c);
|
|
|
-- serial engine --
|
-- serial engine --
|
if (rtx_engine.state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled
|
rtx_engine.state(2) <= ctrl(ctrl_en_c);
|
-- --------------------------------------------------------------
|
case rtx_engine.state is
|
spi_sck_o <= ctrl(ctrl_spi_cpol_c);
|
|
|
when "100" => -- enabled but idle, waiting for new transmission trigger
|
|
-- ------------------------------------------------------------
|
rtx_engine.bitcnt <= (others => '0');
|
rtx_engine.bitcnt <= (others => '0');
|
rtx_engine.state1 <= '0';
|
if (rtx_engine.start = '1') then -- trigger new transmission
|
if (ctrl(ctrl_spi_en_c) = '0') then -- disabled
|
rtx_engine.sreg <= data_i;
|
rtx_engine.busy <= '0';
|
rtx_engine.state(1 downto 0) <= "01";
|
elsif (wren = '1') and (addr = spi_rtx_addr_c) then -- start new transmission
|
end if;
|
rtx_engine.rtx_sreg <= data_i;
|
|
rtx_engine.busy <= '1';
|
when "101" => -- start with next new clock pulse
|
end if;
|
-- ------------------------------------------------------------
|
rtx_engine.state0 <= rtx_engine.busy and spi_clk_en; -- start with next new clock pulse
|
|
|
|
else -- transmission in progress
|
|
-- --------------------------------------------------------------
|
|
|
|
if (rtx_engine.state1 = '0') then -- first half of bit transmission
|
|
-- --------------------------------------------------------------
|
|
spi_sck_o <= ctrl(ctrl_spi_cpha_c) xor ctrl(ctrl_spi_cpol_c);
|
|
--
|
|
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is
|
|
when "00" => spi_sdo_o <= rtx_engine.rtx_sreg(07); -- 8-bit mode
|
|
when "01" => spi_sdo_o <= rtx_engine.rtx_sreg(15); -- 16-bit mode
|
|
when "10" => spi_sdo_o <= rtx_engine.rtx_sreg(23); -- 24-bit mode
|
|
when others => spi_sdo_o <= rtx_engine.rtx_sreg(31); -- 32-bit mode
|
|
end case;
|
|
--
|
|
if (spi_clk_en = '1') then
|
if (spi_clk_en = '1') then
|
if (ctrl(ctrl_spi_cpha_c) = '0') then
|
rtx_engine.state(1 downto 0) <= "10";
|
rtx_engine.rtx_sreg <= rtx_engine.rtx_sreg(30 downto 0) & rtx_engine.sdi_ff1;
|
|
end if;
|
end if;
|
|
|
|
when "110" => -- first half of bit transmission
|
|
-- ------------------------------------------------------------
|
|
spi_sck_o <= ctrl(ctrl_cpha_c) xor ctrl(ctrl_cpol_c);
|
|
if (spi_clk_en = '1') then
|
rtx_engine.bitcnt <= std_ulogic_vector(unsigned(rtx_engine.bitcnt) + 1);
|
rtx_engine.bitcnt <= std_ulogic_vector(unsigned(rtx_engine.bitcnt) + 1);
|
rtx_engine.state1 <= '1';
|
rtx_engine.state(1 downto 0) <= "11";
|
end if;
|
end if;
|
|
|
else -- second half of bit transmission
|
when "111" => -- second half of bit transmission
|
-- --------------------------------------------------------------
|
-- ------------------------------------------------------------
|
spi_sck_o <= ctrl(ctrl_spi_cpha_c) xnor ctrl(ctrl_spi_cpol_c);
|
spi_sck_o <= ctrl(ctrl_cpha_c) xnor ctrl(ctrl_cpol_c);
|
--
|
|
if (spi_clk_en = '1') then
|
if (spi_clk_en = '1') then
|
if (ctrl(ctrl_spi_cpha_c) = '1') then
|
rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync(rtx_engine.sdi_sync'left);
|
rtx_engine.rtx_sreg <= rtx_engine.rtx_sreg(30 downto 0) & rtx_engine.sdi_ff1;
|
if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred?
|
|
rtx_engine.state(1 downto 0) <= "00";
|
|
else
|
|
rtx_engine.state(1 downto 0) <= "10";
|
end if;
|
end if;
|
if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then
|
|
rtx_engine.state0 <= '0';
|
|
rtx_engine.busy <= '0';
|
|
end if;
|
|
rtx_engine.state1 <= '0';
|
|
end if;
|
end if;
|
|
|
end if;
|
when others => -- "0--": SPI deactivated
|
end if;
|
-- ------------------------------------------------------------
|
|
rtx_engine.state(1 downto 0) <= "00";
|
|
|
|
end case;
|
end if;
|
end if;
|
end process spi_rtx_unit;
|
end process spi_rtx_unit;
|
|
|
|
-- busy flag --
|
|
rtx_engine.busy <= '0' when (rtx_engine.state(1 downto 0) = "00") else '1';
|
|
|
|
|
-- Interrupt ------------------------------------------------------------------------------
|
-- Interrupt ------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
irq_o <= ctrl(ctrl_spi_en_c) and (not rtx_engine.busy); -- fire IRQ if transceiver idle
|
irq_o <= '1' when (rtx_engine.state = "100") else '0'; -- fire IRQ if transceiver idle and enabled
|
|
|
|
|
end neorv32_spi_rtl;
|
end neorv32_spi_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
