| Line 102... |
Line 102... |
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal rden : std_ulogic;
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signal rden : std_ulogic;
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signal wren : std_ulogic;
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signal wren : std_ulogic;
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signal iaddr : std_ulogic_vector(02 downto 0);
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signal addr : std_ulogic_vector(2 downto 0);
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-- system information ROM --
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-- system information ROM --
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type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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signal sysinfo_mem : info_mem_t;
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signal sysinfo_mem : info_mem_t;
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| Line 115... |
Line 115... |
-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
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rden <= acc_en and rden_i; -- read access
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rden <= acc_en and rden_i; -- read access
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wren <= acc_en and wren_i; -- write access
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wren <= acc_en and wren_i; -- write access
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iaddr <= addr_i(index_size_f(sysinfo_size_c)-1 downto 2);
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addr <= addr_i(index_size_f(sysinfo_size_c)-1 downto 2);
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-- Construct Info ROM ---------------------------------------------------------------------
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-- Construct Info ROM ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- SYSINFO(0): Processor (primary) clock frequency --
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-- SYSINFO(0): Processor (primary) clock frequency --
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| Line 189... |
Line 189... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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read_access: process(clk_i)
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read_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= rden;
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ack_o <= rden;
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err_o <= wren;
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err_o <= wren; -- read-only!
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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data_o <= sysinfo_mem(to_integer(unsigned(iaddr)));
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data_o <= sysinfo_mem(to_integer(unsigned(addr)));
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else
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data_o <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process read_access;
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end process read_access;
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