| Line 46... |
Line 46... |
|
|
entity neorv32_top is
|
entity neorv32_top is
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
| Line 96... |
Line 96... |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO (available if IO_GPIO_USE = true) --
|
-- GPIO (available if IO_GPIO_USE = true) --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_USE = true) --
|
-- UART (available if IO_UART_USE = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
| Line 120... |
Line 123... |
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
|
|
architecture neorv32_top_rtl of neorv32_top is
|
architecture neorv32_top_rtl of neorv32_top is
|
|
|
|
-- CPU boot address --
|
|
constant boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_USE, boot_base_c, MEM_ISPACE_BASE);
|
|
|
-- reset generator --
|
-- reset generator --
|
signal rstn_i_sync0 : std_ulogic;
|
signal rstn_i_sync0 : std_ulogic;
|
signal rstn_i_sync1 : std_ulogic;
|
signal rstn_i_sync1 : std_ulogic;
|
signal rstn_i_sync2 : std_ulogic;
|
signal rstn_i_sync2 : std_ulogic;
|
signal rstn_gen : std_ulogic_vector(3 downto 0);
|
signal rstn_gen : std_ulogic_vector(3 downto 0);
|
| Line 139... |
Line 145... |
signal uart_cg_en : std_ulogic;
|
signal uart_cg_en : std_ulogic;
|
signal spi_cg_en : std_ulogic;
|
signal spi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
|
|
-- cpu bus --
|
-- bus interface --
|
type cpu_bus_t is record
|
type bus_interface_t is record
|
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
we : std_ulogic; -- write enable
|
we : std_ulogic; -- write enable
|
re : std_ulogic; -- read enable
|
re : std_ulogic; -- read enable
|
cancel : std_ulogic; -- cancel current transfer
|
cancel : std_ulogic; -- cancel current transfer
|
ack : std_ulogic; -- bus transfer acknowledge
|
ack : std_ulogic; -- bus transfer acknowledge
|
err : std_ulogic; -- bus transfer error
|
err : std_ulogic; -- bus transfer error
|
|
fence : std_ulogic; -- fence(i) instruction executed
|
end record;
|
end record;
|
signal cpu : cpu_bus_t;
|
signal cpu_i, cpu_d, p_bus : bus_interface_t;
|
|
|
-- io space access --
|
-- io space access --
|
signal io_acc : std_ulogic;
|
signal io_acc : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_wren : std_ulogic;
|
signal io_wren : std_ulogic;
|
| Line 188... |
Line 195... |
signal clic_ack : std_ulogic;
|
signal clic_ack : std_ulogic;
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_ack : std_ulogic;
|
signal trng_ack : std_ulogic;
|
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal devnull_ack : std_ulogic;
|
signal devnull_ack : std_ulogic;
|
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
|
signal sysinfo_ack : std_ulogic;
|
|
|
-- IRQs --
|
-- IRQs --
|
signal mtime_irq : std_ulogic;
|
signal mtime_irq : std_ulogic;
|
signal clic_irq : std_ulogic;
|
signal clic_irq : std_ulogic;
|
signal clic_xirq : std_ulogic_vector(7 downto 0);
|
signal clic_xirq : std_ulogic_vector(7 downto 0);
|
| Line 225... |
Line 234... |
if (MEM_INT_IMEM_USE = false) and (BOOTLOADER_USE = false) then
|
if (MEM_INT_IMEM_USE = false) and (BOOTLOADER_USE = false) then
|
assert false report "NEORV32 CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- memory system - address space --
|
-- memory system --
|
if (MEM_INT_IMEM_USE = true) and (MEM_INT_IMEM_SIZE > MEM_ISPACE_SIZE) then
|
if (MEM_INT_IMEM_USE = true) and (MEM_INT_IMEM_SIZE > MEM_ISPACE_SIZE) then
|
assert false report "NEORV32 CONFIG ERROR! Internal instruction memory (IMEM) cannot be greater than total instruction address space." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Internal instruction memory (IMEM) cannot be greater than total instruction address space." severity error;
|
end if;
|
end if;
|
if (MEM_INT_DMEM_USE = true) and (MEM_INT_DMEM_SIZE > MEM_DSPACE_SIZE) then
|
if (MEM_INT_DMEM_USE = true) and (MEM_INT_DMEM_SIZE > MEM_DSPACE_SIZE) then
|
assert false report "NEORV32 CONFIG ERROR! Internal data memory (DMEM) cannot be greater than total data address space." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Internal data memory (DMEM) cannot be greater than total data address space." severity error;
|
end if;
|
end if;
|
if (MEM_EXT_TIMEOUT <= 1) then
|
if (MEM_EXT_TIMEOUT < 1) then
|
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Internal components require 1 cycle delay." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Processor-internal components have 1 cycle delay." severity error;
|
end if;
|
end if;
|
|
|
-- clock --
|
-- clock --
|
if (CLOCK_FREQUENCY = 0) then
|
if (CLOCK_FREQUENCY = 0) then
|
assert false report "NEORV32 CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
|
end if;
|
end if;
|
|
|
-- CSR system not implemented --
|
-- CSR system not implemented --
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine status features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
end if;
|
end if;
|
-- core local interrupt controller --
|
-- core local interrupt controller --
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
|
assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error;
|
assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error;
|
end if;
|
end if;
|
|
|
-- memory layout notifier --
|
-- memory layout notifier --
|
if (MEM_ISPACE_BASE /= x"00000000") then
|
if (MEM_ISPACE_BASE /= x"00000000") then
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the linker script." severity warning;
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
|
end if;
|
end if;
|
if (MEM_DSPACE_BASE /= x"80000000") then
|
if (MEM_DSPACE_BASE /= x"80000000") then
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the linker script." severity warning;
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framwork." severity warning;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sanity_check;
|
end process sanity_check;
|
|
|
|
|
| Line 319... |
Line 328... |
-- CPU ------------------------------------------------------------------------------------
|
-- CPU ------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_inst: neorv32_cpu
|
neorv32_cpu_inst: neorv32_cpu
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
|
HART_ID => HART_ID, -- custom hardware thread ID
|
|
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID => (others => '0'), -- hardware thread id
|
|
CPU_BOOT_ADDR => boot_addr_c, -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
|
|
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after which a valid bus access will timeout
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
|
|
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
-- bus interface --
|
-- instruction bus interface --
|
bus_addr_o => cpu.addr, -- bus access address
|
i_bus_addr_o => cpu_i.addr, -- bus access address
|
bus_rdata_i => cpu.rdata, -- bus read data
|
i_bus_rdata_i => cpu_i.rdata, -- bus read data
|
bus_wdata_o => cpu.wdata, -- bus write data
|
i_bus_wdata_o => cpu_i.wdata, -- bus write data
|
bus_ben_o => cpu.ben, -- byte enable
|
i_bus_ben_o => cpu_i.ben, -- byte enable
|
bus_we_o => cpu.we, -- write enable
|
i_bus_we_o => cpu_i.we, -- write enable
|
bus_re_o => cpu.re, -- read enable
|
i_bus_re_o => cpu_i.re, -- read enable
|
bus_cancel_o => cpu.cancel, -- cancel current bus transaction
|
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction
|
bus_ack_i => cpu.ack, -- bus transfer acknowledge
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
bus_err_i => cpu.err, -- bus transfer error
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
|
-- data bus interface --
|
|
d_bus_addr_o => cpu_d.addr, -- bus access address
|
|
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
|
d_bus_we_o => cpu_d.we, -- write enable
|
|
d_bus_re_o => cpu_d.re, -- read enable
|
|
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction
|
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => mtime_time, -- current system time
|
time_i => mtime_time, -- current system time
|
-- external interrupts --
|
-- external interrupts --
|
|
msw_irq_i => '0', -- software interrupt
|
clic_irq_i => clic_irq, -- CLIC interrupt request
|
clic_irq_i => clic_irq, -- CLIC interrupt request
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
);
|
);
|
|
|
-- CPU data input --
|
|
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
|
|
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
|
|
|
|
-- CPU ACK input --
|
|
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
|
|
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
|
|
|
|
-- CPU bus error input --
|
-- CPU Crossbar Switch --------------------------------------------------------------------
|
cpu.err <= wishbone_err;
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_busswitch_inst: neorv32_busswitch
|
|
generic map (
|
|
PORT_CA_READ_ONLY => false, -- set if controller port A is read-only
|
|
PORT_CB_READ_ONLY => true -- set if controller port B is read-only
|
|
)
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
|
-- controller interface a --
|
|
ca_bus_addr_i => cpu_d.addr, -- bus access address
|
|
ca_bus_rdata_o => cpu_d.rdata, -- bus read data
|
|
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
|
ca_bus_we_i => cpu_d.we, -- write enable
|
|
ca_bus_re_i => cpu_d.re, -- read enable
|
|
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction
|
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
|
-- controller interface b --
|
|
cb_bus_addr_i => cpu_i.addr, -- bus access address
|
|
cb_bus_rdata_o => cpu_i.rdata, -- bus read data
|
|
cb_bus_wdata_i => cpu_i.wdata, -- bus write data
|
|
cb_bus_ben_i => cpu_i.ben, -- byte enable
|
|
cb_bus_we_i => cpu_i.we, -- write enable
|
|
cb_bus_re_i => cpu_i.re, -- read enable
|
|
cb_bus_cancel_i => cpu_i.cancel, -- cancel current bus transaction
|
|
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
|
cb_bus_err_o => cpu_i.err, -- bus transfer error
|
|
-- peripheral bus --
|
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
|
p_bus_rdata_i => p_bus.rdata, -- bus read data
|
|
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
|
p_bus_we_o => p_bus.we, -- write enable
|
|
p_bus_re_o => p_bus.re, -- read enable
|
|
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
|
p_bus_err_i => p_bus.err -- bus transfer error
|
|
);
|
|
|
|
-- advanced memory control --
|
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
|
-- process bus: CPU data input --
|
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
|
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
|
|
|
|
-- process bus: CPU data ACK input --
|
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
|
|
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack);
|
|
|
|
-- process bus: CPU data bus error input --
|
|
p_bus.err <= wishbone_err;
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_imem_inst_true:
|
neorv32_int_imem_inst_true:
|
| Line 401... |
Line 447... |
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
|
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
|
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
|
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
wren_i => cpu.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
upen_i => '1', -- update enable
|
upen_i => '1', -- update enable
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => imem_rdata, -- data out
|
data_o => imem_rdata, -- data out
|
ack_o => imem_ack -- transfer acknowledge
|
ack_o => imem_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 430... |
Line 476... |
DMEM_BASE => MEM_DSPACE_BASE, -- memory base address
|
DMEM_BASE => MEM_DSPACE_BASE, -- memory base address
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
wren_i => cpu.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => dmem_rdata, -- data out
|
data_o => dmem_rdata, -- data out
|
ack_o => dmem_ack -- transfer acknowledge
|
ack_o => dmem_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 454... |
Line 500... |
neorv32_boot_rom_inst_true:
|
neorv32_boot_rom_inst_true:
|
if (BOOTLOADER_USE = true) generate
|
if (BOOTLOADER_USE = true) generate
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_o => bootrom_rdata, -- data out
|
data_o => bootrom_rdata, -- data out
|
ack_o => bootrom_ack -- transfer acknowledge
|
ack_o => bootrom_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 491... |
Line 537... |
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset line, low-active
|
rstn_i => sys_rstn, -- global reset line, low-active
|
-- host access --
|
-- host access --
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => cpu.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
wren_i => cpu.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => wishbone_rdata, -- data out
|
data_o => wishbone_rdata, -- data out
|
cancel_i => cpu.cancel, -- cancel current transaction
|
cancel_i => p_bus.cancel, -- cancel current transaction
|
ack_o => wishbone_ack, -- transfer acknowledge
|
ack_o => wishbone_ack, -- transfer acknowledge
|
err_o => wishbone_err, -- transfer error
|
err_o => wishbone_err, -- transfer error
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_adr_o => wb_adr_o, -- address
|
wb_adr_o => wb_adr_o, -- address
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_i => wb_dat_i, -- read data
|
| Line 530... |
Line 576... |
end generate;
|
end generate;
|
|
|
|
|
-- IO Access? -----------------------------------------------------------------------------
|
-- IO Access? -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_rden <= io_acc and cpu.re;
|
io_rden <= io_acc and p_bus.re;
|
io_wren <= io_acc and cpu.we;
|
io_wren <= io_acc and p_bus.we;
|
|
|
|
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_gpio_inst_true:
|
neorv32_gpio_inst_true:
|
if (IO_GPIO_USE = true) generate
|
if (IO_GPIO_USE = true) generate
|
neorv32_gpio_inst: neorv32_gpio
|
neorv32_gpio_inst: neorv32_gpio
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => gpio_rdata, -- data out
|
data_o => gpio_rdata, -- data out
|
ack_o => gpio_ack, -- transfer acknowledge
|
ack_o => gpio_ack, -- transfer acknowledge
|
-- parallel io --
|
-- parallel io --
|
gpio_o => gpio_o,
|
gpio_o => gpio_o,
|
gpio_i => gpio_i,
|
gpio_i => gpio_i,
|
| Line 577... |
Line 623... |
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => clic_rdata, -- data out
|
data_o => clic_rdata, -- data out
|
ack_o => clic_ack, -- transfer acknowledge
|
ack_o => clic_ack, -- transfer acknowledge
|
-- cpu interrupt --
|
-- cpu interrupt --
|
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
|
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
|
-- external interrupt lines --
|
-- external interrupt lines --
|
| Line 624... |
Line 670... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => wdt_rdata, -- data out
|
data_o => wdt_rdata, -- data out
|
ack_o => wdt_ack, -- transfer acknowledge
|
ack_o => wdt_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => wdt_cg_en, -- enable clock generator
|
clkgen_en_o => wdt_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 657... |
Line 703... |
neorv32_mtime_inst: neorv32_mtime
|
neorv32_mtime_inst: neorv32_mtime
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => mtime_rdata, -- data out
|
data_o => mtime_rdata, -- data out
|
ack_o => mtime_ack, -- transfer acknowledge
|
ack_o => mtime_ack, -- transfer acknowledge
|
-- time output for CPU --
|
-- time output for CPU --
|
time_o => mtime_time, -- current system time
|
time_o => mtime_time, -- current system time
|
-- interrupt --
|
-- interrupt --
|
| Line 688... |
Line 734... |
if (IO_UART_USE = true) generate
|
if (IO_UART_USE = true) generate
|
neorv32_uart_inst: neorv32_uart
|
neorv32_uart_inst: neorv32_uart
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => uart_rdata, -- data out
|
data_o => uart_rdata, -- data out
|
ack_o => uart_ack, -- transfer acknowledge
|
ack_o => uart_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 724... |
Line 770... |
if (IO_SPI_USE = true) generate
|
if (IO_SPI_USE = true) generate
|
neorv32_spi_inst: neorv32_spi
|
neorv32_spi_inst: neorv32_spi
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => spi_rdata, -- data out
|
data_o => spi_rdata, -- data out
|
ack_o => spi_ack, -- transfer acknowledge
|
ack_o => spi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 764... |
Line 810... |
if (IO_TWI_USE = true) generate
|
if (IO_TWI_USE = true) generate
|
neorv32_twi_inst: neorv32_twi
|
neorv32_twi_inst: neorv32_twi
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => twi_rdata, -- data out
|
data_o => twi_rdata, -- data out
|
ack_o => twi_ack, -- transfer acknowledge
|
ack_o => twi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 801... |
Line 847... |
if (IO_PWM_USE = true) generate
|
if (IO_PWM_USE = true) generate
|
neorv32_pwm_inst: neorv32_pwm
|
neorv32_pwm_inst: neorv32_pwm
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => pwm_rdata, -- data out
|
data_o => pwm_rdata, -- data out
|
ack_o => pwm_ack, -- transfer acknowledge
|
ack_o => pwm_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 833... |
Line 879... |
if (IO_TRNG_USE = true) generate
|
if (IO_TRNG_USE = true) generate
|
neorv32_trng_inst: neorv32_trng
|
neorv32_trng_inst: neorv32_trng
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => trng_rdata, -- data out
|
data_o => trng_rdata, -- data out
|
ack_o => trng_ack -- transfer acknowledge
|
ack_o => trng_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 858... |
Line 904... |
if (IO_DEVNULL_USE = true) generate
|
if (IO_DEVNULL_USE = true) generate
|
neorv32_devnull_inst: neorv32_devnull
|
neorv32_devnull_inst: neorv32_devnull
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => cpu.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => devnull_rdata, -- data out
|
data_o => devnull_rdata, -- data out
|
ack_o => devnull_ack -- transfer acknowledge
|
ack_o => devnull_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 875... |
Line 921... |
devnull_rdata <= (others => '0');
|
devnull_rdata <= (others => '0');
|
devnull_ack <= '0';
|
devnull_ack <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
|
-- System Configuration Information Memory (SYSINFO) --------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_sysinfo_inst: neorv32_sysinfo
|
|
generic map (
|
|
-- General --
|
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
|
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
|
|
USER_CODE => USER_CODE, -- custom user code
|
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
|
|
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
|
|
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
|
)
|
|
port map (
|
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-- host access --
|
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clk_i => clk_i, -- global clock line
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
data_o => sysinfo_rdata, -- data out
|
|
ack_o => sysinfo_ack -- transfer acknowledge
|
|
);
|
|
|
|
|
end neorv32_top_rtl;
|
end neorv32_top_rtl;
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No newline at end of file
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No newline at end of file
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