| Line 585... |
Line 585... |
clic_xirq(4) <= spi_irq;
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clic_xirq(4) <= spi_irq;
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clic_xirq(5) <= twi_irq;
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clic_xirq(5) <= twi_irq;
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clic_xirq(6) <= ext_irq_i(0);
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clic_xirq(6) <= ext_irq_i(0);
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clic_xirq(7) <= ext_irq_i(1); -- lowest priority
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clic_xirq(7) <= ext_irq_i(1); -- lowest priority
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|
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ext_ack_o <= clic_xirq(7 downto 6); -- external interrupt request acknowledge
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-- external interrupt request acknowledge --
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ext_ack_o(0) <= clic_xack(6);
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ext_ack_o(1) <= clic_xack(7);
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|
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neorv32_clic_inst_false:
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neorv32_clic_inst_false:
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if (IO_CLIC_USE = false) generate
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if (IO_CLIC_USE = false) generate
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clic_rdata <= (others => '0');
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clic_rdata <= (others => '0');
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clic_ack <= '0';
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clic_ack <= '0';
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| Line 639... |
Line 641... |
if (IO_MTIME_USE = true) generate
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if (IO_MTIME_USE = true) generate
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neorv32_mtime_inst: neorv32_mtime
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neorv32_mtime_inst: neorv32_mtime
|
port map (
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port map (
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-- host access --
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-- host access --
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clk_i => clk_i, -- global clock line
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clk_i => clk_i, -- global clock line
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rstn_i => sys_rstn, -- global reset, low-active, async
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addr_i => cpu_addr, -- address
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addr_i => cpu_addr, -- address
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rden_i => io_rden, -- read enable
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rden_i => io_rden, -- read enable
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wren_i => io_wren, -- write enable
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wren_i => io_wren, -- write enable
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ben_i => cpu_ben, -- byte write enable
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ben_i => cpu_ben, -- byte write enable
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data_i => cpu_wdata, -- data in
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data_i => cpu_wdata, -- data in
|
