| Line 50... |
Line 50... |
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
|
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
|
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
|
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
|
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
|
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
|
|
-- Internal Cache memory --
|
-- Internal Cache memory --
|
ICACHE_EN : boolean := false; -- implement instruction cache
|
ICACHE_EN : boolean := false; -- implement instruction cache
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
|
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
|
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
| Line 98... |
Line 108... |
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
| Line 110... |
Line 121... |
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
|
|
-- GPIO (available if IO_GPIO_EN = true) --
|
-- GPIO (available if IO_GPIO_EN = true) --
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_EN = true) --
|
|
uart_txd_o : out std_ulogic; -- UART send data
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
|
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
|
|
|
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
|
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
|
|
|
-- SPI (available if IO_SPI_EN = true) --
|
-- SPI (available if IO_SPI_EN = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
|
|
|
-- TWI (available if IO_TWI_EN = true) --
|
-- TWI (available if IO_TWI_EN = true) --
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
|
|
-- PWM (available if IO_PWM_EN = true) --
|
-- PWM (available if IO_PWM_EN = true) --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
|
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CFS inputs conduit
|
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CFS inputs conduit
|
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CFS outputs conduit
|
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CFS outputs conduit
|
|
|
-- NCO output (available if IO_NCO_EN = true) --
|
-- NCO output (available if IO_NCO_EN = true) --
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
|
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
|
|
-- Interrupts --
|
-- Interrupts --
|
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
| Line 170... |
Line 195... |
|
|
-- clock generator --
|
-- clock generator --
|
signal clk_div : std_ulogic_vector(11 downto 0);
|
signal clk_div : std_ulogic_vector(11 downto 0);
|
signal clk_div_ff : std_ulogic_vector(11 downto 0);
|
signal clk_div_ff : std_ulogic_vector(11 downto 0);
|
signal clk_gen : std_ulogic_vector(07 downto 0);
|
signal clk_gen : std_ulogic_vector(07 downto 0);
|
|
signal clk_gen_en : std_ulogic_vector(07 downto 0);
|
--
|
--
|
signal wdt_cg_en : std_ulogic;
|
signal wdt_cg_en : std_ulogic;
|
signal uart_cg_en : std_ulogic;
|
signal uart0_cg_en : std_ulogic;
|
|
signal uart1_cg_en : std_ulogic;
|
signal spi_cg_en : std_ulogic;
|
signal spi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
signal cfs_cg_en : std_ulogic;
|
signal cfs_cg_en : std_ulogic;
|
signal nco_cg_en : std_ulogic;
|
signal nco_cg_en : std_ulogic;
|
| Line 216... |
Line 243... |
signal wishbone_err : std_ulogic;
|
signal wishbone_err : std_ulogic;
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_ack : std_ulogic;
|
signal gpio_ack : std_ulogic;
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_ack : std_ulogic;
|
signal mtime_ack : std_ulogic;
|
signal uart_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal uart_ack : std_ulogic;
|
signal uart0_ack : std_ulogic;
|
|
signal uart1_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
|
signal uart1_ack : std_ulogic;
|
signal spi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal spi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal spi_ack : std_ulogic;
|
signal spi_ack : std_ulogic;
|
signal twi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal twi_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal twi_ack : std_ulogic;
|
signal twi_ack : std_ulogic;
|
signal pwm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal pwm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
| Line 229... |
Line 258... |
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wdt_ack : std_ulogic;
|
signal wdt_ack : std_ulogic;
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_ack : std_ulogic;
|
signal trng_ack : std_ulogic;
|
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal cfs_err : std_ulogic;
|
|
signal cfs_ack : std_ulogic;
|
signal cfs_ack : std_ulogic;
|
signal nco_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal nco_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal nco_ack : std_ulogic;
|
signal nco_ack : std_ulogic;
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_ack : std_ulogic;
|
signal sysinfo_ack : std_ulogic;
|
| Line 244... |
Line 272... |
signal fast_irq : std_ulogic_vector(15 downto 0);
|
signal fast_irq : std_ulogic_vector(15 downto 0);
|
signal fast_irq_ack : std_ulogic_vector(15 downto 0);
|
signal fast_irq_ack : std_ulogic_vector(15 downto 0);
|
--
|
--
|
signal gpio_irq : std_ulogic;
|
signal gpio_irq : std_ulogic;
|
signal wdt_irq : std_ulogic;
|
signal wdt_irq : std_ulogic;
|
signal uart_rxd_irq : std_ulogic;
|
signal uart0_rxd_irq : std_ulogic;
|
signal uart_txd_irq : std_ulogic;
|
signal uart0_txd_irq : std_ulogic;
|
|
signal uart1_rxd_irq : std_ulogic;
|
|
signal uart1_txd_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
signal cfs_irq : std_ulogic;
|
signal cfs_irq : std_ulogic;
|
signal cfs_irq_ack : std_ulogic;
|
signal cfs_irq_ack : std_ulogic;
|
|
|
| Line 317... |
Line 347... |
clock_generator: process(sys_rstn, clk_i)
|
clock_generator: process(sys_rstn, clk_i)
|
begin
|
begin
|
if (sys_rstn = '0') then
|
if (sys_rstn = '0') then
|
clk_div <= (others => '0');
|
clk_div <= (others => '0');
|
clk_div_ff <= (others => '0');
|
clk_div_ff <= (others => '0');
|
|
clk_gen_en <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- fresh clocks anyone? --
|
-- fresh clocks anyone? --
|
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfs_cg_en or nco_cg_en) = '1') then
|
clk_gen_en(0) <= wdt_cg_en;
|
|
clk_gen_en(1) <= uart0_cg_en;
|
|
clk_gen_en(2) <= uart1_cg_en;
|
|
clk_gen_en(3) <= spi_cg_en;
|
|
clk_gen_en(4) <= twi_cg_en;
|
|
clk_gen_en(5) <= pwm_cg_en;
|
|
clk_gen_en(6) <= cfs_cg_en;
|
|
clk_gen_en(7) <= nco_cg_en;
|
|
if (or_all_f(clk_gen_en) = '1') then
|
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
|
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
|
end if;
|
end if;
|
clk_div_ff <= clk_div;
|
clk_div_ff <= clk_div;
|
end if;
|
end if;
|
end process clock_generator;
|
end process clock_generator;
|
| Line 420... |
Line 459... |
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
-- fast interrupts - processor-internal --
|
-- fast interrupts - processor-internal --
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(01) <= '0'; -- reserved
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(02) <= cfs_irq; -- custom functions subsystem
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
|
fast_irq(03) <= uart_rxd_irq; -- UART data received
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
|
fast_irq(04) <= uart_txd_irq; -- UART transmission done
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received
|
fast_irq(05) <= spi_irq; -- SPI transmission done
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done
|
fast_irq(06) <= twi_irq; -- TWI transmission done
|
fast_irq(06) <= spi_irq; -- SPI transmission done
|
fast_irq(07) <= gpio_irq; -- GPIO pin-change
|
fast_irq(07) <= twi_irq; -- TWI transmission done
|
|
fast_irq(08) <= gpio_irq; -- GPIO pin-change
|
|
fast_irq(09) <= '0'; -- reserved
|
|
|
-- fast interrupts - platform level (for custom use) --
|
-- fast interrupts - platform level (for custom use) --
|
fast_irq(08) <= soc_firq_i(0);
|
fast_irq(10) <= soc_firq_i(0);
|
fast_irq(09) <= soc_firq_i(1);
|
fast_irq(11) <= soc_firq_i(1);
|
fast_irq(10) <= soc_firq_i(2);
|
fast_irq(12) <= soc_firq_i(2);
|
fast_irq(11) <= soc_firq_i(3);
|
fast_irq(13) <= soc_firq_i(3);
|
fast_irq(12) <= soc_firq_i(4);
|
fast_irq(14) <= soc_firq_i(4);
|
fast_irq(13) <= soc_firq_i(5);
|
fast_irq(15) <= soc_firq_i(5);
|
fast_irq(14) <= soc_firq_i(6);
|
|
fast_irq(15) <= soc_firq_i(7);
|
|
|
|
-- IRQ acknowledge --
|
-- IRQ acknowledge --
|
cfs_irq_ack <= fast_irq_ack(2);
|
cfs_irq_ack <= fast_irq_ack(2);
|
|
|
|
|
| Line 545... |
Line 584... |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_err_i => p_bus.err -- bus transfer error
|
p_bus_err_i => p_bus.err -- bus transfer error
|
);
|
);
|
|
|
-- processor bus: CPU transfer data input --
|
-- processor bus: CPU transfer data input --
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or sysinfo_rdata);
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or sysinfo_rdata);
|
|
|
-- processor bus: CPU transfer ACK input --
|
-- processor bus: CPU transfer ACK input --
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or sysinfo_ack);
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or sysinfo_ack);
|
|
|
-- processor bus: CPU transfer data bus error input --
|
-- processor bus: CPU transfer data bus error input --
|
p_bus.err <= wishbone_err or cfs_err;
|
p_bus.err <= wishbone_err;
|
|
|
-- current CPU privilege level --
|
-- current CPU privilege level --
|
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv
|
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv
|
|
|
|
|
| Line 731... |
Line 770... |
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- byte write enable
|
wren_i => io_wren, -- byte write enable
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => cfs_rdata, -- data out
|
data_o => cfs_rdata, -- data out
|
ack_o => cfs_ack, -- transfer acknowledge
|
ack_o => cfs_ack, -- transfer acknowledge
|
err_o => cfs_err, -- transfer error
|
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => cfs_cg_en, -- enable clock generator
|
clkgen_en_o => cfs_cg_en, -- enable clock generator
|
clkgen_i => clk_gen, -- "clock" inputs
|
clkgen_i => clk_gen, -- "clock" inputs
|
-- CPU state --
|
-- CPU state --
|
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
|
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
|
| Line 750... |
Line 788... |
|
|
neorv32_cfs_inst_false:
|
neorv32_cfs_inst_false:
|
if (IO_CFS_EN = false) generate
|
if (IO_CFS_EN = false) generate
|
cfs_rdata <= (others => '0');
|
cfs_rdata <= (others => '0');
|
cfs_ack <= '0';
|
cfs_ack <= '0';
|
cfs_err <= '0';
|
|
cfs_cg_en <= '0';
|
cfs_cg_en <= '0';
|
cfs_irq <= '0';
|
cfs_irq <= '0';
|
cfs_out_o <= (others => '0');
|
cfs_out_o <= (others => '0');
|
end generate;
|
end generate;
|
|
|
| Line 853... |
Line 890... |
mtime_ack <= '0';
|
mtime_ack <= '0';
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
end generate;
|
end generate;
|
|
|
|
|
-- Universal Asynchronous Receiver/Transmitter (UART) -------------------------------------
|
-- Universal Asynchronous Receiver/Transmitter 0, Primary UART (UART0) --------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_uart_inst_true:
|
neorv32_uart0_inst_true:
|
if (IO_UART_EN = true) generate
|
if (IO_UART0_EN = true) generate
|
neorv32_uart_inst: neorv32_uart
|
neorv32_uart0_inst: neorv32_uart
|
|
generic map (
|
|
UART_PRIMARY => true -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
)
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
data_i => p_bus.wdata, -- data in
|
|
data_o => uart0_rdata, -- data out
|
|
ack_o => uart0_ack, -- transfer acknowledge
|
|
-- clock generator --
|
|
clkgen_en_o => uart0_cg_en, -- enable clock generator
|
|
clkgen_i => clk_gen,
|
|
-- com lines --
|
|
uart_txd_o => uart0_txd_o,
|
|
uart_rxd_i => uart0_rxd_i,
|
|
-- interrupts --
|
|
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
|
|
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
|
|
);
|
|
end generate;
|
|
|
|
neorv32_uart0_inst_false:
|
|
if (IO_UART0_EN = false) generate
|
|
uart0_rdata <= (others => '0');
|
|
uart0_ack <= '0';
|
|
uart0_txd_o <= '0';
|
|
uart0_cg_en <= '0';
|
|
uart0_rxd_irq <= '0';
|
|
uart0_txd_irq <= '0';
|
|
end generate;
|
|
|
|
|
|
-- Universal Asynchronous Receiver/Transmitter 1, Secondary UART (UART1) ------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_uart1_inst_true:
|
|
if (IO_UART1_EN = true) generate
|
|
neorv32_uart1_inst: neorv32_uart
|
|
generic map (
|
|
UART_PRIMARY => false -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
)
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => uart_rdata, -- data out
|
data_o => uart1_rdata, -- data out
|
ack_o => uart_ack, -- transfer acknowledge
|
ack_o => uart1_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_en_o => uart1_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
-- com lines --
|
-- com lines --
|
uart_txd_o => uart_txd_o,
|
uart_txd_o => uart1_txd_o,
|
uart_rxd_i => uart_rxd_i,
|
uart_rxd_i => uart1_rxd_i,
|
-- interrupts --
|
-- interrupts --
|
irq_rxd_o => uart_rxd_irq, -- uart data received interrupt
|
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
|
irq_txd_o => uart_txd_irq -- uart transmission done interrupt
|
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_uart_inst_false:
|
neorv32_uart1_inst_false:
|
if (IO_UART_EN = false) generate
|
if (IO_UART1_EN = false) generate
|
uart_rdata <= (others => '0');
|
uart1_rdata <= (others => '0');
|
uart_ack <= '0';
|
uart1_ack <= '0';
|
uart_txd_o <= '0';
|
uart1_txd_o <= '0';
|
uart_cg_en <= '0';
|
uart1_cg_en <= '0';
|
uart_rxd_irq <= '0';
|
uart1_rxd_irq <= '0';
|
uart_txd_irq <= '0';
|
uart1_txd_irq <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- Serial Peripheral Interface (SPI) ------------------------------------------------------
|
-- Serial Peripheral Interface (SPI) ------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1076... |
Line 1156... |
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_UART_EN => IO_UART_EN, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
