| Line 58... |
Line 58... |
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
|
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
| Line 93... |
Line 93... |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
|
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
|
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
|
|
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
| Line 117... |
Line 118... |
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_tag_i : in std_ulogic := '0'; -- response tag
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
| Line 188... |
Line 189... |
architecture neorv32_top_rtl of neorv32_top is
|
architecture neorv32_top_rtl of neorv32_top is
|
|
|
-- CPU boot address --
|
-- CPU boot address --
|
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
|
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
|
|
|
-- Bus timeout --
|
|
constant bus_timeout_temp_c : natural := 2**index_size_f(bus_timeout_c); -- round to next power-of-two
|
|
constant bus_timeout_proc_c : natural := cond_sel_natural_f(ICACHE_EN, ((ICACHE_BLOCK_SIZE/4)*bus_timeout_temp_c)-1, bus_timeout_c);
|
|
|
|
-- alignment check for internal memories --
|
-- alignment check for internal memories --
|
constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
|
constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
|
constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
|
constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
|
|
|
-- reset generator --
|
-- reset generator --
|
| Line 229... |
Line 226... |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
we : std_ulogic; -- write enable
|
we : std_ulogic; -- write enable
|
re : std_ulogic; -- read enable
|
re : std_ulogic; -- read enable
|
cancel : std_ulogic; -- cancel current transfer
|
|
ack : std_ulogic; -- bus transfer acknowledge
|
ack : std_ulogic; -- bus transfer acknowledge
|
err : std_ulogic; -- bus transfer error
|
err : std_ulogic; -- bus transfer error
|
fence : std_ulogic; -- fence(i) instruction executed
|
fence : std_ulogic; -- fence(i) instruction executed
|
priv : std_ulogic_vector(1 downto 0); -- current privilege level
|
priv : std_ulogic_vector(1 downto 0); -- current privilege level
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
excl : std_ulogic; -- exclusive access
|
lock : std_ulogic; -- exclusive access request
|
end record;
|
end record;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
signal cpu_d_exclr : std_ulogic; -- CPU D-bus, exclusive access response
|
|
|
|
-- io space access --
|
-- io space access --
|
signal io_acc : std_ulogic;
|
signal io_acc : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_wren : std_ulogic;
|
signal io_wren : std_ulogic;
|
| Line 255... |
Line 250... |
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bootrom_ack : std_ulogic;
|
signal bootrom_ack : std_ulogic;
|
signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wishbone_ack : std_ulogic;
|
signal wishbone_ack : std_ulogic;
|
signal wishbone_err : std_ulogic;
|
signal wishbone_err : std_ulogic;
|
signal wishbone_exclr : std_ulogic;
|
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_ack : std_ulogic;
|
signal gpio_ack : std_ulogic;
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_ack : std_ulogic;
|
signal mtime_ack : std_ulogic;
|
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
| Line 282... |
Line 276... |
signal nco_ack : std_ulogic;
|
signal nco_ack : std_ulogic;
|
signal neoled_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal neoled_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal neoled_ack : std_ulogic;
|
signal neoled_ack : std_ulogic;
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_ack : std_ulogic;
|
signal sysinfo_ack : std_ulogic;
|
|
signal bus_keeper_err : std_ulogic;
|
|
|
-- IRQs --
|
-- IRQs --
|
signal mtime_irq : std_ulogic;
|
signal mtime_irq : std_ulogic;
|
--
|
--
|
signal fast_irq : std_ulogic_vector(15 downto 0);
|
signal fast_irq : std_ulogic_vector(15 downto 0);
|
| Line 330... |
Line 325... |
-- memory system - layout warning --
|
-- memory system - layout warning --
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
-- memory system - cached instruction fetch latency check --
|
|
assert not (ICACHE_EN = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing i-cache. Increasing bus access timeout from " & integer'image(bus_timeout_c) & " cycles to " & integer'image(bus_timeout_proc_c) & " cycles." severity warning;
|
|
|
|
|
|
-- Reset Generator ------------------------------------------------------------------------
|
-- Reset Generator ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
reset_generator_sync: process(clk_i)
|
reset_generator_sync: process(clk_i)
|
begin
|
begin
|
| Line 409... |
Line 401... |
neorv32_cpu_inst: neorv32_cpu
|
neorv32_cpu_inst: neorv32_cpu
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address
|
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address
|
BUS_TIMEOUT => bus_timeout_proc_c, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
| Line 443... |
Line 434... |
i_bus_rdata_i => cpu_i.rdata, -- bus read data
|
i_bus_rdata_i => cpu_i.rdata, -- bus read data
|
i_bus_wdata_o => cpu_i.wdata, -- bus write data
|
i_bus_wdata_o => cpu_i.wdata, -- bus write data
|
i_bus_ben_o => cpu_i.ben, -- byte enable
|
i_bus_ben_o => cpu_i.ben, -- byte enable
|
i_bus_we_o => cpu_i.we, -- write enable
|
i_bus_we_o => cpu_i.we, -- write enable
|
i_bus_re_o => cpu_i.re, -- read enable
|
i_bus_re_o => cpu_i.re, -- read enable
|
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction
|
i_bus_lock_o => cpu_i.lock, -- exclusive access request
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
i_bus_priv_o => cpu_i.priv, -- privilege level
|
i_bus_priv_o => cpu_i.priv, -- privilege level
|
-- data bus interface --
|
-- data bus interface --
|
| Line 455... |
Line 446... |
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
d_bus_we_o => cpu_d.we, -- write enable
|
d_bus_we_o => cpu_d.we, -- write enable
|
d_bus_re_o => cpu_d.re, -- read enable
|
d_bus_re_o => cpu_d.re, -- read enable
|
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction
|
d_bus_lock_o => cpu_d.lock, -- exclusive access request
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
d_bus_excl_o => cpu_d.excl, -- exclusive access
|
|
d_bus_excl_i => cpu_d_exclr, -- state of exclusiv access (set if success)
|
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => mtime_time, -- current system time
|
time_i => mtime_time, -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
| Line 474... |
Line 463... |
firq_i => fast_irq, -- fast interrupt trigger
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask
|
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask
|
);
|
);
|
|
|
-- misc --
|
-- misc --
|
cpu_i.excl <= '0'; -- i-fetch cannot do exclusive accesses
|
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
|
|
-- advanced memory control --
|
-- advanced memory control --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
| Line 528... |
Line 516... |
host_rdata_o => cpu_i.rdata, -- bus read data
|
host_rdata_o => cpu_i.rdata, -- bus read data
|
host_wdata_i => cpu_i.wdata, -- bus write data
|
host_wdata_i => cpu_i.wdata, -- bus write data
|
host_ben_i => cpu_i.ben, -- byte enable
|
host_ben_i => cpu_i.ben, -- byte enable
|
host_we_i => cpu_i.we, -- write enable
|
host_we_i => cpu_i.we, -- write enable
|
host_re_i => cpu_i.re, -- read enable
|
host_re_i => cpu_i.re, -- read enable
|
host_cancel_i => cpu_i.cancel, -- cancel current bus transaction
|
|
host_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
host_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
host_err_o => cpu_i.err, -- bus transfer error
|
host_err_o => cpu_i.err, -- bus transfer error
|
-- peripheral bus interface --
|
-- peripheral bus interface --
|
bus_addr_o => i_cache.addr, -- bus access address
|
bus_addr_o => i_cache.addr, -- bus access address
|
bus_rdata_i => i_cache.rdata, -- bus read data
|
bus_rdata_i => i_cache.rdata, -- bus read data
|
bus_wdata_o => i_cache.wdata, -- bus write data
|
bus_wdata_o => i_cache.wdata, -- bus write data
|
bus_ben_o => i_cache.ben, -- byte enable
|
bus_ben_o => i_cache.ben, -- byte enable
|
bus_we_o => i_cache.we, -- write enable
|
bus_we_o => i_cache.we, -- write enable
|
bus_re_o => i_cache.re, -- read enable
|
bus_re_o => i_cache.re, -- read enable
|
bus_cancel_o => i_cache.cancel, -- cancel current bus transaction
|
|
bus_ack_i => i_cache.ack, -- bus transfer acknowledge
|
bus_ack_i => i_cache.ack, -- bus transfer acknowledge
|
bus_err_i => i_cache.err -- bus transfer error
|
bus_err_i => i_cache.err -- bus transfer error
|
);
|
);
|
end generate;
|
end generate;
|
|
|
|
-- TODO: do not use LOCKED instruction fetch --
|
|
i_cache.lock <= '0';
|
|
|
neorv32_icache_inst_false:
|
neorv32_icache_inst_false:
|
if (ICACHE_EN = false) generate
|
if (ICACHE_EN = false) generate
|
i_cache.addr <= cpu_i.addr;
|
i_cache.addr <= cpu_i.addr;
|
cpu_i.rdata <= i_cache.rdata;
|
cpu_i.rdata <= i_cache.rdata;
|
i_cache.wdata <= cpu_i.wdata;
|
i_cache.wdata <= cpu_i.wdata;
|
i_cache.ben <= cpu_i.ben;
|
i_cache.ben <= cpu_i.ben;
|
i_cache.we <= cpu_i.we;
|
i_cache.we <= cpu_i.we;
|
i_cache.re <= cpu_i.re;
|
i_cache.re <= cpu_i.re;
|
i_cache.cancel <= cpu_i.cancel;
|
|
cpu_i.ack <= i_cache.ack;
|
cpu_i.ack <= i_cache.ack;
|
cpu_i.err <= i_cache.err;
|
cpu_i.err <= i_cache.err;
|
end generate;
|
end generate;
|
|
|
-- no exclusive accesses for i-fetch --
|
|
i_cache.excl <= '0';
|
|
|
|
|
|
-- CPU Bus Switch -------------------------------------------------------------------------
|
-- CPU Bus Switch -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_busswitch_inst: neorv32_busswitch
|
neorv32_busswitch_inst: neorv32_busswitch
|
generic map (
|
generic map (
|
| Line 579... |
Line 564... |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data
|
ca_bus_rdata_o => cpu_d.rdata, -- bus read data
|
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
ca_bus_we_i => cpu_d.we, -- write enable
|
ca_bus_we_i => cpu_d.we, -- write enable
|
ca_bus_re_i => cpu_d.re, -- read enable
|
ca_bus_re_i => cpu_d.re, -- read enable
|
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction
|
ca_bus_lock_i => cpu_d.lock, -- exclusive access request
|
ca_bus_excl_i => cpu_d.excl, -- exclusive access
|
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
-- controller interface b --
|
-- controller interface b --
|
cb_bus_addr_i => i_cache.addr, -- bus access address
|
cb_bus_addr_i => i_cache.addr, -- bus access address
|
cb_bus_rdata_o => i_cache.rdata, -- bus read data
|
cb_bus_rdata_o => i_cache.rdata, -- bus read data
|
cb_bus_wdata_i => i_cache.wdata, -- bus write data
|
cb_bus_wdata_i => i_cache.wdata, -- bus write data
|
cb_bus_ben_i => i_cache.ben, -- byte enable
|
cb_bus_ben_i => i_cache.ben, -- byte enable
|
cb_bus_we_i => i_cache.we, -- write enable
|
cb_bus_we_i => i_cache.we, -- write enable
|
cb_bus_re_i => i_cache.re, -- read enable
|
cb_bus_re_i => i_cache.re, -- read enable
|
cb_bus_cancel_i => i_cache.cancel, -- cancel current bus transaction
|
cb_bus_lock_i => i_cache.lock, -- exclusive access request
|
cb_bus_excl_i => i_cache.excl, -- exclusive access
|
|
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge
|
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge
|
cb_bus_err_o => i_cache.err, -- bus transfer error
|
cb_bus_err_o => i_cache.err, -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions)
|
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions)
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
p_bus_rdata_i => p_bus.rdata, -- bus read data
|
p_bus_rdata_i => p_bus.rdata, -- bus read data
|
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
p_bus_lock_o => p_bus.lock, -- exclusive access request
|
p_bus_excl_o => p_bus.excl, -- exclusive access
|
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_err_i => p_bus.err -- bus transfer error
|
p_bus_err_i => p_bus.err -- bus transfer error
|
);
|
);
|
|
|
-- static signals --
|
-- static signals --
|
| Line 620... |
Line 602... |
-- processor bus: CPU transfer ACK input --
|
-- processor bus: CPU transfer ACK input --
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack);
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack);
|
|
|
-- processor bus: CPU transfer data bus error input --
|
-- processor bus: CPU transfer data bus error input --
|
p_bus.err <= wishbone_err;
|
p_bus.err <= bus_keeper_err or wishbone_err;
|
|
|
-- exclusive access status --
|
|
-- since all internal modules/memories are only accessible to this CPU internal atomic access cannot fail
|
-- Processor-Internal Bus Keeper (BUSKEEPER) ----------------------------------------------
|
cpu_d_exclr <= wishbone_exclr; -- only external atomic memory accesses can fail
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
|
generic map (
|
|
-- Internal instruction memory --
|
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
|
-- Internal data memory --
|
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
|
|
)
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
rstn_i => sys_rstn, -- global reset line, low-active
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => p_bus.re, -- read enable
|
|
wren_i => p_bus.we, -- write enable
|
|
ack_i => p_bus.ack, -- transfer acknowledge from bus system
|
|
err_i => p_bus.err, -- transfer error from bus system
|
|
err_o => bus_keeper_err -- bus error
|
|
);
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_imem_inst_true:
|
neorv32_int_imem_inst_true:
|
| Line 722... |
Line 724... |
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
|
-- Bus Timeout --
|
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset line, low-active
|
rstn_i => sys_rstn, -- global reset line, low-active
|
| Line 736... |
Line 740... |
rden_i => p_bus.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
wren_i => p_bus.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => wishbone_rdata, -- data out
|
data_o => wishbone_rdata, -- data out
|
cancel_i => p_bus.cancel, -- cancel current transaction
|
lock_i => p_bus.lock, -- exclusive access request
|
excl_i => p_bus.excl, -- exclusive access request
|
|
excl_o => wishbone_exclr, -- state of exclusiv access (set if success)
|
|
ack_o => wishbone_ack, -- transfer acknowledge
|
ack_o => wishbone_ack, -- transfer acknowledge
|
err_o => wishbone_err, -- transfer error
|
err_o => wishbone_err, -- transfer error
|
priv_i => p_bus.priv, -- current CPU privilege level
|
priv_i => p_bus.priv, -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o => wb_tag_o, -- request tag
|
wb_tag_o => wb_tag_o, -- request tag
|
| Line 751... |
Line 753... |
wb_dat_o => wb_dat_o, -- write data
|
wb_dat_o => wb_dat_o, -- write data
|
wb_we_o => wb_we_o, -- read/write
|
wb_we_o => wb_we_o, -- read/write
|
wb_sel_o => wb_sel_o, -- byte enable
|
wb_sel_o => wb_sel_o, -- byte enable
|
wb_stb_o => wb_stb_o, -- strobe
|
wb_stb_o => wb_stb_o, -- strobe
|
wb_cyc_o => wb_cyc_o, -- valid cycle
|
wb_cyc_o => wb_cyc_o, -- valid cycle
|
wb_tag_i => wb_tag_i, -- response tag
|
wb_lock_o => wb_lock_o, -- exclusive access request
|
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
wb_err_i => wb_err_i -- transfer error
|
wb_err_i => wb_err_i -- transfer error
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_wishbone_inst_false:
|
neorv32_wishbone_inst_false:
|
if (MEM_EXT_EN = false) generate
|
if (MEM_EXT_EN = false) generate
|
wishbone_rdata <= (others => '0');
|
wishbone_rdata <= (others => '0');
|
wishbone_ack <= '0';
|
wishbone_ack <= '0';
|
wishbone_err <= '0';
|
wishbone_err <= '0';
|
wishbone_exclr <= '0';
|
|
--
|
--
|
wb_adr_o <= (others => '0');
|
wb_adr_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_we_o <= '0';
|
wb_we_o <= '0';
|
wb_sel_o <= (others => '0');
|
wb_sel_o <= (others => '0');
|
