| Line 48... |
Line 48... |
generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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| Line 101... |
Line 102... |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
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-- UART (available if IO_UART_USE = true) --
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-- UART (available if IO_UART_USE = true) --
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uart_txd_o : out std_ulogic; -- UART send data
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uart_txd_o : out std_ulogic; -- UART send data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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-- SPI (available if IO_SPI_USE = true) --
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-- SPI (available if IO_SPI_USE = true) --
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spi_sclk_o : out std_ulogic; -- serial clock line
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_mosi_o : out std_ulogic; -- serial data line out
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_miso_i : in std_ulogic := '0'; -- serial data line in
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spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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-- TWI (available if IO_TWI_USE = true) --
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-- TWI (available if IO_TWI_USE = true) --
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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-- PWM (available if IO_PWM_USE = true) --
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-- PWM (available if IO_PWM_USE = true) --
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| Line 313... |
Line 314... |
generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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HART_ID => HART_ID, -- custom hardware thread ID
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HART_ID => HART_ID, -- custom hardware thread ID
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
|
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CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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| Line 717... |
Line 719... |
ack_o => spi_ack, -- transfer acknowledge
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ack_o => spi_ack, -- transfer acknowledge
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-- clock generator --
|
-- clock generator --
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clkgen_en_o => spi_cg_en, -- enable clock generator
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clkgen_en_o => spi_cg_en, -- enable clock generator
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clkgen_i => clk_gen,
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clkgen_i => clk_gen,
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-- com lines --
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-- com lines --
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spi_sclk_o => spi_sclk_o, -- SPI serial clock
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spi_sck_o => spi_sck_o, -- SPI serial clock
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spi_mosi_o => spi_mosi_o, -- SPI master out, slave in
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spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
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spi_miso_i => spi_miso_i, -- SPI master in, slave out
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spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
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spi_csn_o => spi_csn_o, -- SPI CS
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spi_csn_o => spi_csn_o, -- SPI CS
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-- interrupt --
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-- interrupt --
|
spi_irq_o => spi_irq -- transmission done interrupt
|
spi_irq_o => spi_irq -- transmission done interrupt
|
);
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);
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end generate;
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end generate;
|
|
|
neorv32_spi_inst_false:
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neorv32_spi_inst_false:
|
if (IO_SPI_USE = false) generate
|
if (IO_SPI_USE = false) generate
|
spi_rdata <= (others => '0');
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spi_rdata <= (others => '0');
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spi_ack <= '0';
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spi_ack <= '0';
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spi_sclk_o <= '0';
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spi_sck_o <= '0';
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spi_mosi_o <= '0';
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spi_sdo_o <= '0';
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spi_csn_o <= (others => '1'); -- CSn lines are low-active
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spi_csn_o <= (others => '1'); -- CSn lines are low-active
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spi_cg_en <= '0';
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spi_cg_en <= '0';
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spi_irq <= '0';
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spi_irq <= '0';
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end generate;
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end generate;
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|
