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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Processor Top Entity >> #
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-- # << NEORV32 - Processor Top Entity >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project #
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-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project #
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-- # and define all the configuration generics according to your needs. Alternatively, you can use #
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-- # and define all the configuration generics according to your needs. Alternatively, you can use #
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-- # one of the alternative top entities provided in the "rtl/top_templates" folder. #
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-- # one of the alternative top entities provided in the "rtl/templates" folder. #
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-- # #
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-- # #
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-- # Check out the processor's documentation for more information. #
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-- # Check out the processor's documentation for more information. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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entity neorv32_top is
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entity neorv32_top is
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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-- Internal Instruction memory --
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-- Internal Instruction memory (IMEM) --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Internal Data memory --
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory --
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-- Internal Cache memory (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface --
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-- External memory interface (WISHBONE) --
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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-- Stream link interface (SLINK) --
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SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
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SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
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SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
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SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
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-- External Interrupts Controller (XIRQ) --
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NCO_EN : boolean := true; -- implement numerically-controlled oscillator (NCO)?
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IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- ready to send
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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slink_rx_dat_i : in sdata_8x32_t := (others => (others => '0')); -- input data
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slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- valid input
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slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
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-- GPIO (available if IO_GPIO_EN = true) --
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
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gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
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gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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-- NCO output (available if IO_NCO_EN = true) --
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nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_ulogic; -- async serial data line
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neoled_o : out std_ulogic; -- async serial data line
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-- System time --
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-- System time --
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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-- Interrupts --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
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-- CPU interrupts --
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nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
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nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
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soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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);
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);
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end neorv32_top;
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end neorv32_top;
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architecture neorv32_top_rtl of neorv32_top is
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architecture neorv32_top_rtl of neorv32_top is
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-- CPU boot address --
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-- CPU boot configuration --
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constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
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constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
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-- alignment check for internal memories --
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-- alignment check for internal memories --
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constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
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constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
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constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
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constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
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-- helpers --
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constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all?
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-- reset generator --
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-- reset generator --
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signal rstn_gen : std_ulogic_vector(7 downto 0);
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signal rstn_gen : std_ulogic_vector(7 downto 0);
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signal ext_rstn : std_ulogic;
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signal ext_rstn : std_ulogic;
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signal sys_rstn : std_ulogic;
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signal sys_rstn : std_ulogic;
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signal wdt_rstn : std_ulogic;
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signal wdt_rstn : std_ulogic;
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-- clock generator --
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-- clock generator --
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signal clk_div : std_ulogic_vector(11 downto 0);
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signal clk_div : std_ulogic_vector(11 downto 0);
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signal clk_div_ff : std_ulogic_vector(11 downto 0);
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signal clk_div_ff : std_ulogic_vector(11 downto 0);
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signal clk_gen : std_ulogic_vector(07 downto 0);
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signal clk_gen : std_ulogic_vector(07 downto 0);
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signal clk_gen_en : std_ulogic_vector(08 downto 0);
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signal clk_gen_en : std_ulogic_vector(07 downto 0);
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--
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--
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signal wdt_cg_en : std_ulogic;
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signal wdt_cg_en : std_ulogic;
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signal uart0_cg_en : std_ulogic;
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signal uart0_cg_en : std_ulogic;
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signal uart1_cg_en : std_ulogic;
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signal uart1_cg_en : std_ulogic;
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signal spi_cg_en : std_ulogic;
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signal spi_cg_en : std_ulogic;
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signal twi_cg_en : std_ulogic;
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signal twi_cg_en : std_ulogic;
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signal pwm_cg_en : std_ulogic;
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signal pwm_cg_en : std_ulogic;
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signal cfs_cg_en : std_ulogic;
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signal cfs_cg_en : std_ulogic;
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signal nco_cg_en : std_ulogic;
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signal neoled_cg_en : std_ulogic;
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signal neoled_cg_en : std_ulogic;
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-- bus interface --
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-- bus interface --
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type bus_interface_t is record
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type bus_interface_t is record
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addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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end record;
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end record;
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constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0');
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constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0');
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-- module response bus - device ID --
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-- module response bus - device ID --
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type resp_bus_id_t is (RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI,
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type resp_bus_id_t is (RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI,
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RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NCO, RESP_NEOLED, RESP_SYSINFO, RESP_OCD);
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RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ);
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-- module response bus --
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-- module response bus --
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type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
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type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
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signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c);
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signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c);
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-- IRQs --
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-- IRQs --
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signal fast_irq : std_ulogic_vector(15 downto 0);
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signal fast_irq : std_ulogic_vector(15 downto 0);
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signal fast_irq_ack : std_ulogic_vector(15 downto 0);
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signal mtime_irq : std_ulogic;
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signal mtime_irq : std_ulogic;
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signal gpio_irq : std_ulogic;
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signal wdt_irq : std_ulogic;
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signal wdt_irq : std_ulogic;
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signal uart0_rxd_irq : std_ulogic;
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signal uart0_rxd_irq : std_ulogic;
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signal uart0_txd_irq : std_ulogic;
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signal uart0_txd_irq : std_ulogic;
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signal uart1_rxd_irq : std_ulogic;
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signal uart1_rxd_irq : std_ulogic;
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signal uart1_txd_irq : std_ulogic;
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signal uart1_txd_irq : std_ulogic;
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signal spi_irq : std_ulogic;
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signal spi_irq : std_ulogic;
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signal twi_irq : std_ulogic;
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signal twi_irq : std_ulogic;
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signal cfs_irq : std_ulogic;
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signal cfs_irq : std_ulogic;
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signal cfs_irq_ack : std_ulogic;
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signal neoled_irq : std_ulogic;
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signal neoled_irq : std_ulogic;
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signal slink_tx_irq : std_ulogic;
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signal slink_rx_irq : std_ulogic;
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signal xirq_irq : std_ulogic;
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-- misc --
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-- misc --
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
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signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
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signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
|
signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
|
|
|
begin
|
begin
|
|
|
|
-- Processor IO/Peripherals Configuration -------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
assert false report
|
|
"NEORV32 PROCESSOR IO Configuration: " &
|
|
cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") &
|
|
cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") &
|
|
cond_sel_string_f(IO_UART0_EN, "UART0 ", "") &
|
|
cond_sel_string_f(IO_UART1_EN, "UART1 ", "") &
|
|
cond_sel_string_f(IO_SPI_EN, "SPI ", "") &
|
|
cond_sel_string_f(IO_TWI_EN, "TWI ", "") &
|
|
cond_sel_string_f(boolean(IO_PWM_NUM_CH > 0), "PWM ", "") &
|
|
cond_sel_string_f(IO_WDT_EN, "WDT ", "") &
|
|
cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") &
|
|
cond_sel_string_f(IO_CFS_EN, "CFS ", "") &
|
|
cond_sel_string_f(io_slink_en_c, "SLINK ", "") &
|
|
cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") &
|
|
cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") &
|
|
""
|
|
severity note;
|
|
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- clock --
|
-- clock --
|
assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
|
assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
|
-- internal bootloader ROM --
|
|
assert not ((BOOTLOADER_EN = true) and (boot_rom_size_c > boot_rom_max_size_c)) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;
|
-- boot configuration --
|
assert not ((BOOTLOADER_EN = true) and (MEM_INT_IMEM_ROM = true)) report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning;
|
assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
|
-- memory system - data/instruction fetch --
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note;
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note;
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
|
--
|
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal IMEM." severity error;
|
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (INT_BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal IMEM and bootloader." severity error;
|
|
|
-- memory system - size --
|
-- memory system - size --
|
assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
|
|
-- memory system - alignment --
|
-- memory system - alignment --
|
assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;
|
assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;
|
assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;
|
assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;
|
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
|
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
|
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
|
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
|
|
|
-- memory system - layout warning --
|
-- memory system - layout warning --
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
|
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
|
|
-- on-chip debugger --
|
-- on-chip debugger --
|
assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing on-chip debugger (OCD)." severity note;
|
assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note;
|
|
|
|
|
-- Reset Generator ------------------------------------------------------------------------
|
-- Reset Generator ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
reset_generator: process(rstn_i, clk_i)
|
reset_generator: process(rstn_i, clk_i)
|
| Line 370... |
Line 418... |
clk_gen_en(2) <= uart1_cg_en;
|
clk_gen_en(2) <= uart1_cg_en;
|
clk_gen_en(3) <= spi_cg_en;
|
clk_gen_en(3) <= spi_cg_en;
|
clk_gen_en(4) <= twi_cg_en;
|
clk_gen_en(4) <= twi_cg_en;
|
clk_gen_en(5) <= pwm_cg_en;
|
clk_gen_en(5) <= pwm_cg_en;
|
clk_gen_en(6) <= cfs_cg_en;
|
clk_gen_en(6) <= cfs_cg_en;
|
clk_gen_en(7) <= nco_cg_en;
|
clk_gen_en(7) <= neoled_cg_en;
|
clk_gen_en(8) <= neoled_cg_en;
|
|
-- actual clock generator --
|
-- actual clock generator --
|
if (or_reduce_f(clk_gen_en) = '1') then
|
if (or_reduce_f(clk_gen_en) = '1') then
|
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
|
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
|
end if;
|
end if;
|
-- clock enables: rising edge detectors --
|
-- clock enables: rising edge detectors --
|
| Line 407... |
Line 454... |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
| Line 458... |
Line 506... |
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_ack_o => fast_irq_ack, -- fast interrupt acknowledge mask
|
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i => dci_halt_req
|
db_halt_req_i => dci_halt_req
|
);
|
);
|
|
|
-- misc --
|
-- misc --
|
| Line 471... |
Line 518... |
|
|
-- advanced memory control --
|
-- advanced memory control --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
-- fast interrupts - processor-internal --
|
-- fast interrupts --
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done
|
fast_irq(06) <= spi_irq; -- SPI transmission done
|
fast_irq(06) <= spi_irq; -- SPI transmission done
|
fast_irq(07) <= twi_irq; -- TWI transmission done
|
fast_irq(07) <= twi_irq; -- TWI transmission done
|
fast_irq(08) <= gpio_irq; -- GPIO pin-change
|
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
|
fast_irq(10) <= slink_rx_irq; -- SLINK data received
|
-- fast interrupts - platform level (for custom use) --
|
fast_irq(11) <= slink_tx_irq; -- SLINK data send
|
soc_firq_sync: process(clk_i)
|
--
|
begin
|
fast_irq(15 downto 12) <= (others => '0'); -- reserved
|
if rising_edge(clk_i) then -- make sure they are sync
|
|
fast_irq(10) <= soc_firq_i(0);
|
|
fast_irq(11) <= soc_firq_i(1);
|
|
fast_irq(12) <= soc_firq_i(2);
|
|
fast_irq(13) <= soc_firq_i(3);
|
|
fast_irq(14) <= soc_firq_i(4);
|
|
fast_irq(15) <= soc_firq_i(5);
|
|
end if;
|
|
end process soc_firq_sync;
|
|
|
|
-- CFS IRQ acknowledge --
|
|
cfs_irq_ack <= fast_irq_ack(1);
|
|
|
|
|
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_icache_inst_true:
|
neorv32_icache_inst_true:
|
| Line 656... |
Line 691... |
if (MEM_INT_IMEM_EN = true) generate
|
if (MEM_INT_IMEM_EN = true) generate
|
neorv32_int_imem_inst: neorv32_imem
|
neorv32_int_imem_inst: neorv32_imem
|
generic map (
|
generic map (
|
IMEM_BASE => imem_base_c, -- memory base address
|
IMEM_BASE => imem_base_c, -- memory base address
|
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
|
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
|
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
|
IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory?
|
BOOTLOADER_EN => BOOTLOADER_EN -- implement and use bootloader?
|
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => p_bus.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
wren_i => p_bus.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
| Line 709... |
Line 743... |
|
|
|
|
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
|
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_boot_rom_inst_true:
|
neorv32_boot_rom_inst_true:
|
if (BOOTLOADER_EN = true) generate
|
if (INT_BOOTLOADER_EN = true) generate
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
generic map (
|
generic map (
|
BOOTROM_BASE => boot_rom_base_c, -- boot ROM base address
|
BOOTROM_BASE => boot_rom_base_c -- boot ROM base address
|
BOOTROM_SIZE => boot_rom_size_c -- processor-internal boot TOM memory size in bytes
|
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => p_bus.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
| Line 726... |
Line 759... |
);
|
);
|
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
|
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
|
end generate;
|
end generate;
|
|
|
neorv32_boot_rom_inst_false:
|
neorv32_boot_rom_inst_false:
|
if (BOOTLOADER_EN = false) generate
|
if (INT_BOOTLOADER_EN = false) generate
|
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
|
end generate;
|
end generate;
|
|
|
|
|
-- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
|
-- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_wishbone_inst_true:
|
neorv32_wishbone_inst_true:
|
if (MEM_EXT_EN = true) generate
|
if (MEM_EXT_EN = true) generate
|
neorv32_wishbone_inst: neorv32_wishbone
|
neorv32_wishbone_inst: neorv32_wishbone
|
generic map (
|
generic map (
|
WB_PIPELINED_MODE => wb_pipe_mode_c, -- false: classic/standard wishbone mode, true: pipelined wishbone mode
|
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
| Line 828... |
Line 860... |
clkgen_i => clk_gen, -- "clock" inputs
|
clkgen_i => clk_gen, -- "clock" inputs
|
-- CPU state --
|
-- CPU state --
|
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
|
sleep_i => cpu_sleep, -- set if cpu is in sleep mode
|
-- interrupt --
|
-- interrupt --
|
irq_o => cfs_irq, -- interrupt request
|
irq_o => cfs_irq, -- interrupt request
|
irq_ack_i => cfs_irq_ack, -- interrupt acknowledge
|
|
-- custom io (conduit) --
|
-- custom io (conduit) --
|
cfs_in_i => cfs_in_i, -- custom inputs
|
cfs_in_i => cfs_in_i, -- custom inputs
|
cfs_out_o => cfs_out_o -- custom outputs
|
cfs_out_o => cfs_out_o -- custom outputs
|
);
|
);
|
resp_bus(RESP_CFS).err <= '0'; -- no access error possible
|
resp_bus(RESP_CFS).err <= '0'; -- no access error possible
|
| Line 861... |
Line 892... |
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => resp_bus(RESP_GPIO).rdata, -- data out
|
data_o => resp_bus(RESP_GPIO).rdata, -- data out
|
ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge
|
ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge
|
-- parallel io --
|
-- parallel io --
|
gpio_o => gpio_o,
|
gpio_o => gpio_o,
|
gpio_i => gpio_i,
|
gpio_i => gpio_i
|
-- interrupt --
|
|
irq_o => gpio_irq -- pin-change interrupt
|
|
);
|
);
|
resp_bus(RESP_GPIO).err <= '0'; -- no access error possible
|
resp_bus(RESP_GPIO).err <= '0'; -- no access error possible
|
end generate;
|
end generate;
|
|
|
neorv32_gpio_inst_false:
|
neorv32_gpio_inst_false:
|
if (IO_GPIO_EN = false) generate
|
if (IO_GPIO_EN = false) generate
|
resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c;
|
gpio_o <= (others => '0');
|
gpio_o <= (others => '0');
|
gpio_irq <= '0';
|
|
end generate;
|
end generate;
|
|
|
|
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1157... |
Line 1185... |
pwm_cg_en <= '0';
|
pwm_cg_en <= '0';
|
pwm_o <= (others => '0');
|
pwm_o <= (others => '0');
|
end generate;
|
end generate;
|
|
|
|
|
-- Numerically-Controlled Oscillator (NCO) ------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_nco_inst_true:
|
|
if (IO_NCO_EN = true) generate
|
|
neorv32_nco_inst: neorv32_nco
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
data_i => p_bus.wdata, -- data in
|
|
data_o => resp_bus(RESP_NCO).rdata, -- data out
|
|
ack_o => resp_bus(RESP_NCO).ack, -- transfer acknowledge
|
|
-- clock generator --
|
|
clkgen_en_o => nco_cg_en, -- enable clock generator
|
|
clkgen_i => clk_gen,
|
|
-- NCO output --
|
|
nco_o => nco_o
|
|
);
|
|
resp_bus(RESP_NCO).err <= '0'; -- no access error possible
|
|
end generate;
|
|
|
|
neorv32_nco_inst_false:
|
|
if (IO_NCO_EN = false) generate
|
|
resp_bus(RESP_NCO) <= resp_bus_entry_terminate_c;
|
|
nco_cg_en <= '0';
|
|
nco_o <= (others => '0');
|
|
end generate;
|
|
|
|
|
|
-- True Random Number Generator (TRNG) ----------------------------------------------------
|
-- True Random Number Generator (TRNG) ----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_trng_inst_true:
|
neorv32_trng_inst_true:
|
if (IO_TRNG_EN = true) generate
|
if (IO_TRNG_EN = true) generate
|
neorv32_trng_inst: neorv32_trng
|
neorv32_trng_inst: neorv32_trng
|
| Line 1246... |
Line 1243... |
neoled_irq <= '0';
|
neoled_irq <= '0';
|
neoled_o <= '0';
|
neoled_o <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
|
-- Stream Link Interface (SLINK) ----------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_slink_inst_true:
|
|
if (io_slink_en_c = true) generate
|
|
neorv32_slink_inst: neorv32_slink
|
|
generic map (
|
|
SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8)
|
|
SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8)
|
|
SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two
|
|
SLINK_RX_FIFO => SLINK_RX_FIFO -- RX fifo depth, has to be a power of two
|
|
)
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
data_i => p_bus.wdata, -- data in
|
|
data_o => resp_bus(RESP_SLINK).rdata, -- data out
|
|
ack_o => resp_bus(RESP_SLINK).ack, -- transfer acknowledge
|
|
-- interrupt --
|
|
irq_tx_o => slink_tx_irq, -- transmission done
|
|
irq_rx_o => slink_rx_irq, -- data received
|
|
-- TX stream interfaces --
|
|
slink_tx_dat_o => slink_tx_dat_o, -- output data
|
|
slink_tx_val_o => slink_tx_val_o, -- valid output
|
|
slink_tx_rdy_i => slink_tx_rdy_i, -- ready to send
|
|
-- RX stream interfaces --
|
|
slink_rx_dat_i => slink_rx_dat_i, -- input data
|
|
slink_rx_val_i => slink_rx_val_i, -- valid input
|
|
slink_rx_rdy_o => slink_rx_rdy_o -- ready to receive
|
|
);
|
|
resp_bus(RESP_SLINK).err <= '0'; -- no access error possible
|
|
end generate;
|
|
|
|
neorv32_slink_inst_false:
|
|
if (io_slink_en_c = false) generate
|
|
resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c;
|
|
slink_tx_irq <= '0';
|
|
slink_rx_irq <= '0';
|
|
slink_tx_dat_o <= (others => (others => '0'));
|
|
slink_tx_val_o <= (others => '0');
|
|
slink_rx_rdy_o <= (others => '0');
|
|
end generate;
|
|
|
|
|
|
-- External Interrupt Controller (XIRQ) ---------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_xirq_inst_true:
|
|
if (XIRQ_NUM_CH > 0) generate
|
|
neorv32_slink_inst: neorv32_xirq
|
|
generic map (
|
|
XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32)
|
|
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE, -- trigger type: 0=level, 1=edge
|
|
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
|
)
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
addr_i => p_bus.addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
data_i => p_bus.wdata, -- data in
|
|
data_o => resp_bus(RESP_XIRQ).rdata, -- data out
|
|
ack_o => resp_bus(RESP_XIRQ).ack, -- transfer acknowledge
|
|
-- external interrupt lines --
|
|
xirq_i => xirq_i,
|
|
-- CPU interrupt --
|
|
cpu_irq_o => xirq_irq
|
|
);
|
|
resp_bus(RESP_XIRQ).err <= '0'; -- no access error possible
|
|
end generate;
|
|
|
|
neorv32_xirq_inst_false:
|
|
if (XIRQ_NUM_CH = 0) generate
|
|
resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c;
|
|
xirq_irq <= '0';
|
|
end generate;
|
|
|
|
|
-- System Configuration Information Memory (SYSINFO) --------------------------------------
|
-- System Configuration Information Memory (SYSINFO) --------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_sysinfo_inst: neorv32_sysinfo
|
neorv32_sysinfo_inst: neorv32_sysinfo
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
BOOTLOADER_EN => BOOTLOADER_EN, -- implement processor-internal bootloader?
|
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
|
USER_CODE => USER_CODE, -- custom user code
|
USER_CODE => USER_CODE, -- custom user code
|
-- internal Instruction memory --
|
-- internal Instruction memory --
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
|
|
-- Internal Data memory --
|
-- Internal Data memory --
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
-- Internal Cache memory --
|
-- Internal Cache memory --
|
ICACHE_EN => ICACHE_EN, -- implement instruction cache
|
ICACHE_EN => ICACHE_EN, -- implement instruction cache
|
| Line 1281... |
Line 1357... |
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
IO_NCO_EN => IO_NCO_EN, -- implement numerically-controlled oscillator (NCO)?
|
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface?
|
IO_NEOLED_EN => IO_NEOLED_EN -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
|
IO_XIRQ_NUM_CH => XIRQ_NUM_CH -- number of external interrupt (XIRQ) channels to implement
|
)
|
)
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
