| Line 274... |
Line 274... |
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
lock : std_ulogic; -- exclusive access request
|
lock : std_ulogic; -- exclusive access request
|
end record;
|
end record;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
|
|
|
-- bus access error (from BUSKEEPER) --
|
|
signal bus_error : std_ulogic;
|
|
|
-- debug core interface (DCI) --
|
-- debug core interface (DCI) --
|
signal dci_ndmrstn : std_ulogic;
|
signal dci_ndmrstn : std_ulogic;
|
signal dci_halt_req : std_ulogic;
|
signal dci_halt_req : std_ulogic;
|
|
|
-- debug module interface (DMI) --
|
-- debug module interface (DMI) --
|
| Line 333... |
Line 336... |
signal xirq_irq : std_ulogic;
|
signal xirq_irq : std_ulogic;
|
signal gptmr_irq : std_ulogic;
|
signal gptmr_irq : std_ulogic;
|
|
|
-- misc --
|
-- misc --
|
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
|
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
|
|
signal ext_timeout : std_ulogic;
|
|
signal ext_access : std_ulogic;
|
|
|
begin
|
begin
|
|
|
-- Processor IO/Peripherals Configuration -------------------------------------------------
|
-- Processor IO/Peripherals Configuration -------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 529... |
Line 534... |
|
|
-- advanced memory control --
|
-- advanced memory control --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
-- fast interrupts --
|
-- fast interrupt requests (FIRQs) --
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
-- these stay asserted until explicitly acknowledged --
|
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX interrupt
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX interrupt
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX interrupt
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX interrupt
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX
|
fast_irq(06) <= spi_irq; -- SPI idle
|
fast_irq(06) <= spi_irq; -- SPI
|
fast_irq(07) <= twi_irq; -- TWI idle
|
fast_irq(07) <= twi_irq; -- TWI
|
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
fast_irq(10) <= slink_rx_irq; -- SLINK RX interrupt
|
fast_irq(10) <= slink_rx_irq; -- SLINK RX
|
fast_irq(11) <= slink_tx_irq; -- SLINK TX interrupt
|
fast_irq(11) <= slink_tx_irq; -- SLINK TX
|
fast_irq(12) <= gptmr_irq; -- general purpose timer
|
fast_irq(12) <= gptmr_irq; -- general purpose timer
|
--
|
--
|
fast_irq(13) <= '0'; -- reserved
|
fast_irq(13) <= '0'; -- reserved
|
fast_irq(14) <= '0'; -- reserved
|
fast_irq(14) <= '0'; -- reserved
|
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved
|
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved
|
| Line 642... |
Line 648... |
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_lock_o => p_bus.lock, -- exclusive access request
|
p_bus_lock_o => p_bus.lock, -- exclusive access request
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_err_i => p_bus.err -- bus transfer error
|
p_bus_err_i => bus_error -- bus transfer error
|
);
|
);
|
|
|
-- current CPU privilege level --
|
-- current CPU privilege level --
|
p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv
|
p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv
|
|
|
| Line 674... |
Line 680... |
|
|
|
|
-- Bus Keeper (BUSKEEPER) -----------------------------------------------------------------
|
-- Bus Keeper (BUSKEEPER) -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
generic map (
|
|
-- External memory interface --
|
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
|
-- Internal instruction memory --
|
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
|
-- Internal data memory --
|
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes
|
|
)
|
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset line, low-active, use as async
|
rstn_i => sys_rstn, -- global reset line, low-active, use as async
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- byte write enable
|
wren_i => io_wren, -- byte write enable
|
data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out
|
data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out
|
ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge
|
ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge
|
err_o => resp_bus(RESP_BUSKEEPER).err, -- transfer error
|
err_o => bus_error, -- transfer error
|
-- bus monitoring --
|
-- bus monitoring --
|
bus_addr_i => p_bus.addr, -- address
|
bus_addr_i => p_bus.addr, -- address
|
bus_rden_i => p_bus.re, -- read enable
|
bus_rden_i => p_bus.re, -- read enable
|
bus_wren_i => p_bus.we, -- write enable
|
bus_wren_i => p_bus.we, -- write enable
|
bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system
|
bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system
|
bus_err_i => p_bus.err -- transfer error from bus system
|
bus_err_i => p_bus.err, -- transfer error from bus system
|
|
bus_tmo_i => ext_timeout, -- transfer timeout (external interface)
|
|
bus_ext_i => ext_access -- external bus access
|
);
|
);
|
|
|
|
-- unused, BUSKEEPER **directly** issues error to the CPU --
|
|
resp_bus(RESP_BUSKEEPER).err <= '0';
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_imem_inst_true:
|
neorv32_int_imem_inst_true:
|
if (MEM_INT_IMEM_EN = true) generate
|
if (MEM_INT_IMEM_EN = true) and (MEM_INT_IMEM_SIZE > 0) generate
|
neorv32_int_imem_inst: neorv32_imem
|
neorv32_int_imem_inst: neorv32_imem
|
generic map (
|
generic map (
|
IMEM_BASE => imem_base_c, -- memory base address
|
IMEM_BASE => imem_base_c, -- memory base address
|
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
|
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
|
IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory?
|
IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory?
|
| Line 727... |
Line 728... |
);
|
);
|
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
|
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
|
end generate;
|
end generate;
|
|
|
neorv32_int_imem_inst_false:
|
neorv32_int_imem_inst_false:
|
if (MEM_INT_IMEM_EN = false) generate
|
if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate
|
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
|
end generate;
|
end generate;
|
|
|
|
|
-- Processor-Internal Data Memory (DMEM) --------------------------------------------------
|
-- Processor-Internal Data Memory (DMEM) --------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_dmem_inst_true:
|
neorv32_int_dmem_inst_true:
|
if (MEM_INT_DMEM_EN = true) generate
|
if (MEM_INT_DMEM_EN = true) and (MEM_INT_DMEM_SIZE > 0) generate
|
neorv32_int_dmem_inst: neorv32_dmem
|
neorv32_int_dmem_inst: neorv32_dmem
|
generic map (
|
generic map (
|
DMEM_BASE => dmem_base_c, -- memory base address
|
DMEM_BASE => dmem_base_c, -- memory base address
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
)
|
)
|
| Line 755... |
Line 756... |
);
|
);
|
resp_bus(RESP_DMEM).err <= '0'; -- no access error possible
|
resp_bus(RESP_DMEM).err <= '0'; -- no access error possible
|
end generate;
|
end generate;
|
|
|
neorv32_int_dmem_inst_false:
|
neorv32_int_dmem_inst_false:
|
if (MEM_INT_DMEM_EN = false) generate
|
if (MEM_INT_DMEM_EN = false) or (MEM_INT_DMEM_SIZE = 0) generate
|
resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c;
|
end generate;
|
end generate;
|
|
|
|
|
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
|
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
|
| Line 817... |
Line 818... |
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out
|
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out
|
lock_i => p_bus.lock, -- exclusive access request
|
lock_i => p_bus.lock, -- exclusive access request
|
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge
|
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge
|
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error
|
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error
|
|
tmo_o => ext_timeout, -- transfer timeout
|
priv_i => p_bus.priv, -- current CPU privilege level
|
priv_i => p_bus.priv, -- current CPU privilege level
|
|
ext_o => ext_access, -- active external access
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o => wb_tag_o, -- request tag
|
wb_tag_o => wb_tag_o, -- request tag
|
wb_adr_o => wb_adr_o, -- address
|
wb_adr_o => wb_adr_o, -- address
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_o => wb_dat_o, -- write data
|
wb_dat_o => wb_dat_o, -- write data
|
| Line 836... |
Line 839... |
end generate;
|
end generate;
|
|
|
neorv32_wishbone_inst_false:
|
neorv32_wishbone_inst_false:
|
if (MEM_EXT_EN = false) generate
|
if (MEM_EXT_EN = false) generate
|
resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c;
|
|
ext_timeout <= '0';
|
|
ext_access <= '0';
|
--
|
--
|
wb_adr_o <= (others => '0');
|
wb_adr_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_we_o <= '0';
|
wb_we_o <= '0';
|
wb_sel_o <= (others => '0');
|
wb_sel_o <= (others => '0');
|
| Line 876... |
Line 881... |
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- byte write enable
|
wren_i => io_wren, -- byte write enable
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => resp_bus(RESP_CFS).rdata, -- data out
|
data_o => resp_bus(RESP_CFS).rdata, -- data out
|
ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
|
ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
|
|
err_o => resp_bus(RESP_CFS).err, -- access error
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => cfs_cg_en, -- enable clock generator
|
clkgen_en_o => cfs_cg_en, -- enable clock generator
|
clkgen_i => clk_gen, -- "clock" inputs
|
clkgen_i => clk_gen, -- "clock" inputs
|
-- interrupt --
|
-- interrupt --
|
irq_o => cfs_irq, -- interrupt request
|
irq_o => cfs_irq, -- interrupt request
|
-- custom io (conduit) --
|
-- custom io (conduit) --
|
cfs_in_i => cfs_in_i, -- custom inputs
|
cfs_in_i => cfs_in_i, -- custom inputs
|
cfs_out_o => cfs_out_o -- custom outputs
|
cfs_out_o => cfs_out_o -- custom outputs
|
);
|
);
|
resp_bus(RESP_CFS).err <= '0'; -- no access error possible
|
|
end generate;
|
end generate;
|
|
|
neorv32_cfs_inst_false:
|
neorv32_cfs_inst_false:
|
if (IO_CFS_EN = false) generate
|
if (IO_CFS_EN = false) generate
|
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
|
