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Line 338... |
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-- misc --
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-- misc --
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal ext_timeout : std_ulogic;
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signal ext_timeout : std_ulogic;
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signal ext_access : std_ulogic;
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signal ext_access : std_ulogic;
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signal debug_mode : std_ulogic;
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begin
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begin
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-- Processor IO/Peripherals Configuration -------------------------------------------------
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-- Processor IO/Peripherals Configuration -------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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Line 491... |
port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => sys_rstn, -- global reset, low-active, async
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rstn_i => sys_rstn, -- global reset, low-active, async
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sleep_o => open, -- cpu is in sleep mode when set
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sleep_o => open, -- cpu is in sleep mode when set
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debug_o => debug_mode, -- cpu is in debug mode when set
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-- instruction bus interface --
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-- instruction bus interface --
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i_bus_addr_o => cpu_i.addr, -- bus access address
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i_bus_addr_o => cpu_i.addr, -- bus access address
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i_bus_rdata_i => cpu_i.rdata, -- bus read data
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i_bus_rdata_i => cpu_i.rdata, -- bus read data
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i_bus_wdata_o => cpu_i.wdata, -- bus write data
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i_bus_wdata_o => cpu_i.wdata, -- bus write data
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i_bus_ben_o => cpu_i.ben, -- byte enable
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i_bus_ben_o => cpu_i.ben, -- byte enable
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Line 537... |
-- advanced memory control --
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-- advanced memory control --
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fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
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fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
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fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
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fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
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-- fast interrupt requests (FIRQs) --
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-- fast interrupt requests (FIRQs) --
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-- these stay asserted until explicitly acknowledged --
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-- these signals are single-shot --
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fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
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fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
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fast_irq(01) <= cfs_irq; -- custom functions subsystem
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fast_irq(01) <= cfs_irq; -- custom functions subsystem
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fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
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fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
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fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
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fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
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fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
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fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
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Line 937... |
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
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-- Watch Dog Timer (WDT) ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_wdt_inst_true:
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neorv32_wdt_inst_true:
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if (IO_WDT_EN = true) generate
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if (IO_WDT_EN = true) generate
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neorv32_wdt_inst: neorv32_wdt
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neorv32_wdt_inst: neorv32_wdt
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generic map(
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DEBUG_EN => ON_CHIP_DEBUGGER_EN -- CPU debug mode implemented?
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)
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port map (
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port map (
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-- host access --
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-- host access --
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clk_i => clk_i, -- global clock line
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clk_i => clk_i, -- global clock line
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rstn_i => ext_rstn, -- global reset line, low-active
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rstn_i => ext_rstn, -- global reset line, low-active
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rden_i => io_rden, -- read enable
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rden_i => io_rden, -- read enable
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wren_i => io_wren, -- write enable
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wren_i => io_wren, -- write enable
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addr_i => p_bus.addr, -- address
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addr_i => p_bus.addr, -- address
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data_i => p_bus.wdata, -- data in
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data_i => p_bus.wdata, -- data in
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data_o => resp_bus(RESP_WDT).rdata, -- data out
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data_o => resp_bus(RESP_WDT).rdata, -- data out
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ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge
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ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge
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-- CPU in debug mode? --
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cpu_debug_i => debug_mode,
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-- clock generator --
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-- clock generator --
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clkgen_en_o => wdt_cg_en, -- enable clock generator
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clkgen_en_o => wdt_cg_en, -- enable clock generator
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clkgen_i => clk_gen,
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clkgen_i => clk_gen,
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-- timeout event --
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-- timeout event --
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irq_o => wdt_irq, -- timeout IRQ
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irq_o => wdt_irq, -- timeout IRQ
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