| Line 65... |
Line 65... |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
|
|
|
-- Extension Options --
|
-- Tuning Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
|
|
| Line 203... |
Line 204... |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
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spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
|
|
|
-- TWI (available if IO_TWI_EN = true) --
|
-- TWI (available if IO_TWI_EN = true) --
|
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
|
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
|
|
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
| Line 490... |
Line 491... |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
|
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
|
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
| Line 744... |
Line 746... |
wren_i => p_bus.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => resp_bus(RESP_IMEM).rdata, -- data out
|
data_o => resp_bus(RESP_IMEM).rdata, -- data out
|
ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge
|
ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge
|
|
err_o => resp_bus(RESP_IMEM).err -- transfer error
|
);
|
);
|
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
|
|
end generate;
|
end generate;
|
|
|
neorv32_int_imem_inst_false:
|
neorv32_int_imem_inst_false:
|
if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate
|
if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate
|
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
|
| Line 794... |
Line 796... |
BOOTROM_BASE => boot_rom_base_c -- boot ROM base address
|
BOOTROM_BASE => boot_rom_base_c -- boot ROM base address
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => p_bus.re, -- read enable
|
rden_i => p_bus.re, -- read enable
|
|
wren_i => p_bus.we, -- write enable
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
|
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
|
ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge
|
ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge
|
|
err_o => resp_bus(RESP_BOOTROM).err -- transfer error
|
);
|
);
|
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
|
|
end generate;
|
end generate;
|
|
|
neorv32_boot_rom_inst_false:
|
neorv32_boot_rom_inst_false:
|
if (INT_BOOTLOADER_EN = false) generate
|
if (INT_BOOTLOADER_EN = false) generate
|
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
|
| Line 1494... |
Line 1497... |
neorv32_sysinfo_inst: neorv32_sysinfo
|
neorv32_sysinfo_inst: neorv32_sysinfo
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
|
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
|
|
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
|
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
|
-- Extension Options --
|
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
-- internal Instruction memory --
|
-- internal Instruction memory --
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
