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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_trng.vhd] - Diff between revs 23 and 26
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| Rev 23 |
Rev 26 |
| Line 102... |
Line 102... |
);
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);
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end component;
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end component;
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- full word write enable
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signal wren : std_ulogic; -- full word write enable
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signal rden : std_ulogic; -- read enable
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signal rden : std_ulogic; -- read enable
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-- garo array --
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-- garo array --
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signal garo_en_in : std_ulogic_vector(num_garos_c-1 downto 0);
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signal garo_en_in : std_ulogic_vector(num_garos_c-1 downto 0);
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Line 137... |
begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= trng_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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rden <= acc_en and rden_i;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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