| Line 122... |
Line 122... |
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Total number of ring-oscillators has to be >0." severity error;
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assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Total number of ring-oscillators has to be >0." severity error;
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assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters in fisrt ring has to be odd." severity error;
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assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters in fisrt ring has to be odd." severity error;
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assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters increment for each next ring has to be even." severity error;
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assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters increment for each next ring has to be even." severity error;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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| Line 188... |
Line 189... |
-- John von Neumann De-Biasing ------------------------------------------------------------
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-- John von Neumann De-Biasing ------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neumann_debiasing_sync: process(clk_i)
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neumann_debiasing_sync: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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debiasing.sreg <= debiasing.sreg(debiasing.sreg'left-1 downto 0) & xor_all_f(osc_array_data);
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debiasing.sreg <= debiasing.sreg(debiasing.sreg'left-1 downto 0) & xor_reduce_f(osc_array_data);
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debiasing.state <= (not debiasing.state) and osc_array_en_out(num_roscs_c-1); -- start toggling when last RO is enabled -> process in every second cycle
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debiasing.state <= (not debiasing.state) and osc_array_en_out(num_roscs_c-1); -- start toggling when last RO is enabled -> process in every second cycle
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end if;
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end if;
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end process neumann_debiasing_sync;
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end process neumann_debiasing_sync;
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-- Edge detector --
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-- Edge detector --
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| Line 223... |
Line 224... |
processing.cnt <= (others => '0');
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processing.cnt <= (others => '0');
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else
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else
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processing.cnt <= std_ulogic_vector(unsigned(processing.cnt) + 1);
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processing.cnt <= std_ulogic_vector(unsigned(processing.cnt) + 1);
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end if;
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end if;
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if (lfsr_en_c = true) then -- LFSR post-processing
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if (lfsr_en_c = true) then -- LFSR post-processing
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processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & (xnor_all_f(processing.sreg and lfsr_taps_c) xnor debiasing.data);
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processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & ((not xor_reduce_f(processing.sreg and lfsr_taps_c)) xnor debiasing.data);
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else -- NO post-processing
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else -- NO post-processing
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processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & debiasing.data;
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processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & debiasing.data;
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end if;
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end if;
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end if;
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end if;
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| Line 319... |
Line 320... |
signal enable_sreg : std_ulogic_vector(NUM_INV-1 downto 0); -- enable shift register
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signal enable_sreg : std_ulogic_vector(NUM_INV-1 downto 0); -- enable shift register
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signal sync_ff : std_ulogic_vector(1 downto 0); -- output signal synchronizer
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signal sync_ff : std_ulogic_vector(1 downto 0); -- output signal synchronizer
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not ((NUM_INV mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TNRG.ring_oscillator - Number of inverters in ring has to be odd." severity error;
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-- Ring Oscillator ------------------------------------------------------------------------
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-- Ring Oscillator ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ring_osc: process(enable_i, enable_sreg, inv_chain)
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ring_osc: process(enable_i, enable_sreg, inv_chain)
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begin
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begin
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-- Using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool
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-- Using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool
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