| Line 123... |
Line 123... |
begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Total number of ring-oscillators has to be >0." severity error;
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assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Total number of ring-oscillators has to be >0." severity error;
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assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters in fisrt ring has to be odd." severity error;
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assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters in first ring has to be odd." severity error;
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assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters increment for each next ring has to be even." severity error;
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assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG ERROR: TRNG - Number of inverters increment for each next ring has to be even." severity error;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 259... |
Line 259... |
-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # An inverter chain (ring oscillator) is used as entropy source. #
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-- # An inverter chain (ring oscillator) is used as entropy source. #
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-- # The inverter chain is constructed as an "asynchronous" LFSR. The single inverters are #
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-- # The inverter chain is constructed as an "asynchronous" LFSR. The single inverters are #
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-- # connected via latches that are used to enable/disable the TRNG. Also, these latches are used #
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-- # connected via latches that are used to enable/disable the TRNG. Also, these latches are used #
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-- # as additional delay element. By using unique enable signals for each latch, the synthesis #
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-- # as additional delay element. By using unique enable signals for each latch, the synthesis #
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-- # tool cannot "optimize" (=remove) any of the inverters out of the design. Furthermore, the #
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-- # tool cannot "optimize" (=remove) any of the inverters out of the design. #
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-- # latches prevent the synthesis tool from detecting combinatorial loops. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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