Subversion Repositories neorv32

    );

  end component;

      -- host bus acknowledge --

      end if;

      -- sample --

      if (trng_valid = '1') then

        rnd_reg <= trng_data;

      end if;

      -- data valid? --

      if (enable = '0') then -- disabled

        valid <= '0';

      else

        if (trng_valid = '1') then

          valid <= '1';

        elsif (rden = '1') then

          valid <= '0';

        end if;

  -- neoTRNG --------------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neoTRNG_inst: neoTRNG

    generic map (

      NUM_CELLS     => num_cells_c,

      NUM_INV_START => num_inv_start_c,

      NUM_INV_INC   => num_inv_inc_c,

      NUM_INV_DELAY => num_inv_delay_c

    )

    port map (

      clk_i    => clk_i,

      enable_i => enable,

      data_o   => trng_data,

      valid_o  => trng_valid

    );

end neorv32_trng_rtl;

-- ############################################################################################################################

-- ############################################################################################################################

-- #################################################################################################

-- # << neoTRNG - A Tiny and Platform-Independent True Random Number Generator for any FPGA >>     #

-- # ********************************************************************************************* #

-- # This generator is based on entropy cells, which implement simple ring-oscillators. Each ring- #

-- # oscillator features a short and a long delay path that is dynamically selected defining the   #

-- # primary oscillation frequency. The cells are cascaded so that the random data output of a     #

-- # cell controls the delay path of the next cell (which has the next-larger inverter chain).     #

-- #                                                                                               #

-- # The random data outputs of all cells are XOR-ed and de-biased using a von Neumann randomness  #

-- # extractor (converting edges into bits). The resulting bit is sampled in chunks of 8 bits to   #

-- # provide the final random data output. No further internal post-processing is applied. Hence,  #

-- # the TRNG produces simple de-biased *RAW* data.                                                #

-- #                                                                                               #

-- # The entropy cell architecture uses individually-controlled latches and inverters to create    #

-- # the inverter chain in a platform-agnostic style that can be implemented for any FPGA without  #

-- # requiring primitive instantiation or technology-specific attributes.                          #

-- #                                                                                               #

-- # See the neoTRNG's documentation for more information: https://github.com/stnolting/neoTRNG    #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # neoTRNG - https://github.com/stnolting/neoTRNG                            (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity neoTRNG is

  generic (

    NUM_CELLS     : natural; -- total number of ring-oscillator cells

    NUM_INV_START : natural; -- number of inverters in first cell (short path), has to be odd

    NUM_INV_INC   : natural; -- number of additional inverters in next cell (short path), has to be even

    NUM_INV_DELAY : natural  -- additional inverters to form cell's long path, has to be even

  );

  port (

    clk_i    : in  std_ulogic; -- global clock line

    enable_i : in  std_ulogic; -- unit enable (high-active), reset unit when low

    data_o   : out std_ulogic_vector(7 downto 0); -- random data byte output

    valid_o  : out std_ulogic  -- data_o is valid when set

  );

end neoTRNG;

architecture neoTRNG_rtl of neoTRNG is

  -- Component: neoTRNG entropy cell --

  component neoTRNG_cell

    generic (

      NUM_INV_S : natural; -- number of inverters in short path

      NUM_INV_L : natural  -- number of inverters in long path

    );

    port (

      clk_i    : in  std_ulogic; -- system clock

      select_i : in  std_ulogic; -- delay select

      enable_i : in  std_ulogic; -- enable chain input

      enable_o : out std_ulogic; -- enable chain output

      data_o   : out std_ulogic  -- sync random bit

    );

  end component;

  -- ring-oscillator array interconnect --

  type cell_array_t is record

    en_in  : std_ulogic_vector(NUM_CELLS-1 downto 0);

    en_out : std_ulogic_vector(NUM_CELLS-1 downto 0);

    rnd    : std_ulogic_vector(NUM_CELLS-1 downto 0);

    sel    : std_ulogic_vector(NUM_CELLS-1 downto 0);

  end record;

  signal cell_array : cell_array_t;

  -- global cell-XOR --

  signal rnd_bit : std_ulogic;

  -- von-Neumann de-biasing --

  type debiasing_t is record

    sreg  : std_ulogic_vector(1 downto 0);

    state : std_ulogic; -- process de-biasing every second cycle

    valid : std_ulogic; -- de-biased data

    data  : std_ulogic; -- de-biased data valid

  end record;

  signal deb : debiasing_t;

  -- control unit --

  type ctrl_t is record

    enable : std_ulogic;

    run    : std_ulogic;

    cnt    : std_ulogic_vector(2 downto 0); -- bit counter

    sreg   : std_ulogic_vector(7 downto 0); -- data shift register

  end record;

  signal ctrl : ctrl_t;

begin

  -- Sanity Checks --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  assert not (NUM_CELLS < 2) report "neoTRNG config ERROR: Total number of ring-oscillator cells <NUM_CELLS> has to be >= 2." severity error;

  assert not ((NUM_INV_START mod 2)  = 0) report "neoTRNG config ERROR: Number of inverters in first cell <NUM_INV_START> has to be odd." severity error;

  assert not ((NUM_INV_INC   mod 2) /= 0) report "neoTRNG config ERROR: Inverter increment for each next cell <NUM_INV_INC> has to be even." severity error;

  assert not ((NUM_INV_DELAY mod 2) /= 0) report "neoTRNG config ERROR: Inverter increment to form long path <NUM_INV_DELAY> has to be even." severity error;

      NUM_INV_L => NUM_INV_START + (i*NUM_INV_INC) + NUM_INV_DELAY -- number of inverters in long chain

      data_o   => cell_array.rnd(i) -- SYNC data output

  cell_array.sel(NUM_CELLS-1 downto 1) <= cell_array.rnd(NUM_CELLS-2 downto 0); -- i+1 <= i

  -- enable chain --

  cell_array.en_in(0) <= ctrl.enable; -- start of chain

  cell_array.en_in(NUM_CELLS-1 downto 1) <=cell_array.en_out(NUM_CELLS-2 downto 0); -- i+1 <= i

  -- XOR All Cell's Outputs -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  cell_xor: process(cell_array.rnd)

    variable tmp_v : std_ulogic;

  end process cell_xor;

      deb.state <= (not deb.state) and cell_array.en_out(NUM_CELLS-1);

        ctrl.run <= '0';

      elsif (deb.valid = '1') then -- valid random sample?

        ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) + 1);

        ctrl.run <= '1';

  -- random byte output --

  data_o <= ctrl.sreg;

  -- data valid? --

  valid_o <= '1' when (ctrl.cnt = "000") and (ctrl.run = '1') else '0';

end neoTRNG_rtl;

-- # actually used.                                                                                #

-- #                                                                                               #

-- # Each inverter chain is constructed as an "asynchronous" shift register. The single inverters  #

-- # are connected via latches that are used to enable/disable the TRNG. Also, these latches are   #

-- # used as additional delay element. By using unique enable signals for each latch, the          #

-- # synthesis tool cannot "optimize" (=remove) any of the inverters out of the design making the  #

-- # design platform-agnostic.                                                                     #

    NUM_INV_L : natural  -- number of inverters in long path

    select_i : in  std_ulogic; -- delay select

  signal feedback      : std_ulogic; -- cell feedback/output

  signal enable_sreg_s : std_ulogic_vector(NUM_INV_S-1 downto 0); -- enable shift register for short chain

  signal enable_sreg_l : std_ulogic_vector(NUM_INV_L-1 downto 0); -- enable shift register for long chain

  -- The select_i signals defines which chain is enabled.

  -- NOTE: All signals that control a inverter-latch element have to be registered to ensure a single element

  -- is mapped to a single LUT (or LUT + FF(latch-mode)).

  -- short oscillator chain --

  ring_osc_short: process(enable_i, enable_sreg_s, feedback, inv_chain_s)

  -- long oscillator chain --

  ring_osc_long: process(enable_i, enable_sreg_l, feedback, inv_chain_l)

  begin

    for i in 0 to NUM_INV_L-1 loop -- inverters in long chain

      if (enable_i = '0') then -- start with a defined state (latch reset)

        inv_chain_l(i) <= '0';

      elsif (enable_sreg_l(i) = '1') then

        if (i = NUM_INV_L-1) then -- left-most inverter?

          inv_chain_l(i) <= not feedback;

        else

          inv_chain_l(i) <= not inv_chain_l(i+1);

        end if;

      end if;

    end loop; -- i

  end process ring_osc_long;

  -- length select --

  feedback <= inv_chain_l(0) when (select_i = '0') else inv_chain_s(0);

  -- Using individual enable signals for each inverter from a shift register to prevent the synthesis tool

  -- from removing all but one inverter (since they implement "logical identical functions" (='toggle')).

  -- This makes the TRNG platform independent (since we do not need to use primitives to ensure a correct architecture).

      enable_sreg_l <= enable_sreg_l(enable_sreg_l'left-1 downto 0) & enable_sreg_s(enable_sreg_s'left);

      -- data output sync - no metastability beyond this point --

      sync_ff <= sync_ff(0) & feedback;