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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_twi.vhd] - Diff between revs 6 and 22

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Rev 6 Rev 22
Line 48... Line 48...
    -- host access --
    -- host access --
    clk_i       : in  std_ulogic; -- global clock line
    clk_i       : in  std_ulogic; -- global clock line
    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
    rden_i      : in  std_ulogic; -- read enable
    rden_i      : in  std_ulogic; -- read enable
    wren_i      : in  std_ulogic; -- write enable
    wren_i      : in  std_ulogic; -- write enable
    ben_i       : in  std_ulogic_vector(03 downto 0); -- byte write enable
 
    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
    data_o      : out std_ulogic_vector(31 downto 0); -- data out
    data_o      : out std_ulogic_vector(31 downto 0); -- data out
    ack_o       : out std_ulogic; -- transfer acknowledge
    ack_o       : out std_ulogic; -- transfer acknowledge
    -- clock generator --
    -- clock generator --
    clkgen_en_o : out std_ulogic; -- enable clock generator
    clkgen_en_o : out std_ulogic; -- enable clock generator
Line 127... Line 126...
    if rising_edge(clk_i) then
    if rising_edge(clk_i) then
      ack_o <= acc_en and (rden_i or wren_i);
      ack_o <= acc_en and (rden_i or wren_i);
      -- write access --
      -- write access --
      if (wr_en = '1') then
      if (wr_en = '1') then
        if (addr = twi_ctrl_addr_c) then
        if (addr = twi_ctrl_addr_c) then
          if (ben_i(0) = '1') then
          ctrl <= data_i(ctrl'left downto 0);
            ctrl(07 downto 00) <= data_i(07 downto 00);
 
          end if;
 
        end if;
        end if;
      end if;
      end if;
      -- read access --
      -- read access --
      data_o <= (others => '0');
      data_o <= (others => '0');
      if (rd_en = '1') then
      if (rd_en = '1') then
Line 211... Line 208...
                arbiter(1 downto 0) <= "10";
                arbiter(1 downto 0) <= "10";
              end if;
              end if;
            elsif (addr = twi_rtx_addr_c) then -- start a data transmission
            elsif (addr = twi_rtx_addr_c) then -- start a data transmission
              -- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
              -- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
              -- sampled from peripheral if ctrl_twi_mack_c is cleared
              -- sampled from peripheral if ctrl_twi_mack_c is cleared
              if (ben_i(0) = '1') then
 
                twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
                twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
                arbiter(1 downto 0) <= "11";
                arbiter(1 downto 0) <= "11";
              end if;
              end if;
            end if;
            end if;
          end if;
 
 
 
        when "101" => -- START: generate START condition
        when "101" => -- START: generate START condition
          if (twi_clk_phase(0) = '1') then
          if (twi_clk_phase(0) = '1') then
            twi_sda_o <= '1';
            twi_sda_o <= '1';
          elsif (twi_clk_phase(1) = '1') then
          elsif (twi_clk_phase(1) = '1') then

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