| Line 48... |
Line 48... |
-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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| Line 127... |
Line 126... |
if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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-- write access --
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-- write access --
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if (wr_en = '1') then
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if (wr_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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if (addr = twi_ctrl_addr_c) then
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if (ben_i(0) = '1') then
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ctrl <= data_i(ctrl'left downto 0);
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ctrl(07 downto 00) <= data_i(07 downto 00);
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end if;
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rd_en = '1') then
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if (rd_en = '1') then
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| Line 211... |
Line 208... |
arbiter(1 downto 0) <= "10";
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arbiter(1 downto 0) <= "10";
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end if;
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end if;
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elsif (addr = twi_rtx_addr_c) then -- start a data transmission
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elsif (addr = twi_rtx_addr_c) then -- start a data transmission
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-- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
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-- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
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-- sampled from peripheral if ctrl_twi_mack_c is cleared
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-- sampled from peripheral if ctrl_twi_mack_c is cleared
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if (ben_i(0) = '1') then
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twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
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twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
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arbiter(1 downto 0) <= "11";
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arbiter(1 downto 0) <= "11";
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end if;
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end if;
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end if;
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end if;
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end if;
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when "101" => -- START: generate START condition
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when "101" => -- START: generate START condition
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_sda_o <= '1';
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twi_sda_o <= '1';
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elsif (twi_clk_phase(1) = '1') then
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elsif (twi_clk_phase(1) = '1') then
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