| Line 72... |
Line 72... |
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-- control reg bits --
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-- control reg bits --
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constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_twi_irq_en_c : natural := 3; -- r/w: transmission done interrupt
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constant ctrl_twi_irq_en_c : natural := 3; -- r/w: Enable transmission done interrupt
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constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
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constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
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constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
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constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
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constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
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constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
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constant ctrl_twi_mack_c : natural := 7; -- r/w: generate ACK by controller for transmission
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constant ctrl_twi_mack_c : natural := 7; -- r/w: generate ACK by controller for transmission
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constant ctrl_twi_cksten_c : natural := 8; -- r/w: enable clock stretching by peripheral
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--
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--
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constant ctrl_twi_ack_c : natural := 30; -- r/-: Set if ACK received
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constant ctrl_twi_ack_c : natural := 30; -- r/-: Set if ACK received
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constant ctrl_twi_busy_c : natural := 31; -- r/-: Set if TWI unit is busy
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constant ctrl_twi_busy_c : natural := 31; -- r/-: Set if TWI unit is busy
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-- access control --
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-- access control --
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Line 97... |
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-- twi clock stretching --
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-- twi clock stretching --
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signal twi_clk_halt : std_ulogic;
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signal twi_clk_halt : std_ulogic;
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-- twi transceiver core --
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-- twi transceiver core --
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signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register
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signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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-- tri-state I/O --
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-- tri-state I/O --
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| Line 139... |
Line 140... |
data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
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data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
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data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
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data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_cksten_c) <= ctrl(ctrl_twi_cksten_c);
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--
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--
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data_o(ctrl_twi_ack_c) <= not twi_rtx_sreg(0);
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data_o(ctrl_twi_ack_c) <= not twi_rtx_sreg(0);
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data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
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data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
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else -- twi_rtx_addr_c =>
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else -- twi_rtx_addr_c =>
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data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
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data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
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Line 272... |
end process twi_rtx_unit;
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end process twi_rtx_unit;
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-- Clock Stretching Detector --------------------------------------------------------------
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-- Clock Stretching Detector --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clock_stretching: process(arbiter, twi_scl_o, twi_scl_i_ff1)
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clock_stretching: process(ctrl, arbiter, twi_scl_o, twi_scl_i_ff1)
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begin
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begin
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-- clock stretching by the peripheral can happen at "any time"
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-- clock stretching by the peripheral can happen at "any time"
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if (arbiter(2) = '1') and -- module enabled
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if (arbiter(2) = '1') and -- module enabled
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(ctrl(ctrl_twi_cksten_c) = '1') and -- clock stretching enabled
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(twi_scl_o = '1') and -- controller wants to pull scl high
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(twi_scl_o = '1') and -- controller wants to pull scl high
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(twi_scl_i_ff1 = '0') then -- but scl is pulled low by peripheral
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(twi_scl_i_ff1 = '0') then -- but scl is pulled low by peripheral
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twi_clk_halt <= '1';
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twi_clk_halt <= '1';
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else
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else
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twi_clk_halt <= '0';
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twi_clk_halt <= '0';
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