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Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Two-Wire Interface Controller (TWI) >> #
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-- # << NEORV32 - Two-Wire Interface Controller (TWI) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
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-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
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-- # Supports ACKs by the constroller. No multi-controller support and no peripheral mode support #
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-- # Supports ACKs by the controller. No multi-controller support and no peripheral mode support #
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-- # yet. Interrupt: TWI_transfer_done #
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-- # yet. Interrupt: TWI_idle #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 98... |
Line 98... |
signal twi_clk_halt : std_ulogic;
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signal twi_clk_halt : std_ulogic;
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-- twi transceiver core --
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-- twi transceiver core --
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signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register
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signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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signal rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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-- tri-state I/O --
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-- tri-state I/O --
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signal twi_sda_i_ff0, twi_sda_i_ff1 : std_ulogic; -- sda input sync
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signal twi_sda_i_ff0, twi_sda_i_ff1 : std_ulogic; -- sda input sync
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signal twi_scl_i_ff0, twi_scl_i_ff1 : std_ulogic; -- sda input sync
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signal twi_scl_i_ff0, twi_scl_i_ff1 : std_ulogic; -- sda input sync
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signal twi_sda_i, twi_sda_o : std_ulogic;
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signal twi_sda_i, twi_sda_o : std_ulogic;
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_cksten_c) <= ctrl(ctrl_twi_cksten_c);
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data_o(ctrl_twi_cksten_c) <= ctrl(ctrl_twi_cksten_c);
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--
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--
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data_o(ctrl_twi_ack_c) <= not twi_rtx_sreg(0);
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data_o(ctrl_twi_ack_c) <= not rtx_sreg(0);
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data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
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data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
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else -- twi_rtx_addr_c =>
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else -- twi_rtx_addr_c =>
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data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
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data_o(7 downto 0) <= rtx_sreg(8 downto 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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-- Clock Generation -----------------------------------------------------------------------
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-- Clock Generation -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- clock generator enable --
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-- clock generator enable --
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clkgen_en_o <= ctrl(ctrl_twi_en_c);
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clkgen_en_o <= ctrl(ctrl_twi_en_c);
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-- main twi clock select --
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-- twi clock select --
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twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
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twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
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-- generate four non-overlapping clock ticks at twi_clk/4 --
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-- generate four non-overlapping clock ticks at twi_clk/4 --
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clock_phase_gen: process(clk_i)
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clock_phase_gen: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
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if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
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twi_phase_gen <= "0001"; -- make sure to start with a new phase, 0,1,2,3 stepping
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twi_phase_gen <= "0001"; -- make sure to start with a new phase, bit 0,1,2,3 stepping
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elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
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elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
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twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
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twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- rotate left
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end if;
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end if;
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end if;
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end if;
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end process clock_phase_gen;
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end process clock_phase_gen;
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-- TWI bus signals are set/sampled using 4 clock phases --
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twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
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twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
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twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
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twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
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twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
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twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
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twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
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twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
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irq_o <= '1';
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irq_o <= '1';
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else
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else
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irq_o <= '0';
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irq_o <= '0';
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end if;
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end if;
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-- defaults --
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arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
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-- serial engine --
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-- serial engine --
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-- TWI bus signals are set/sampled using 4 clock phases
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arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
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case arbiter is
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case arbiter is
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when "100" => -- IDLE: waiting for requests, bus might be still claimed by this controller if no STOP condition was generated
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when "100" => -- IDLE: waiting for requests, bus might be still claimed by this controller if no STOP condition was generated
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twi_bitcnt <= (others => '0');
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bitcnt <= (others => '0');
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if (wr_en = '1') then
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if (wr_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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if (addr = twi_ctrl_addr_c) then
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if (data_i(ctrl_twi_start_c) = '1') then -- issue START condition
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if (data_i(ctrl_twi_start_c) = '1') then -- issue START condition
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arbiter(1 downto 0) <= "01";
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arbiter(1 downto 0) <= "01";
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elsif (data_i(ctrl_twi_stop_c) = '1') then -- issue STOP condition
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elsif (data_i(ctrl_twi_stop_c) = '1') then -- issue STOP condition
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arbiter(1 downto 0) <= "10";
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arbiter(1 downto 0) <= "10";
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end if;
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end if;
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elsif (addr = twi_rtx_addr_c) then -- start a data transmission
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elsif (addr = twi_rtx_addr_c) then -- start a data transmission
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-- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
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-- one bit extra for ack, issued by controller if ctrl_twi_mack_c is set,
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-- sampled from peripheral if ctrl_twi_mack_c is cleared
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-- sampled from peripheral if ctrl_twi_mack_c is cleared
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twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
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rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
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arbiter(1 downto 0) <= "11";
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arbiter(1 downto 0) <= "11";
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end if;
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end if;
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end if;
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end if;
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when "101" => -- START: generate START condition
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when "101" => -- START: generate START condition
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_sda_o <= '1';
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twi_sda_o <= '1';
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elsif (twi_clk_phase(1) = '1') then
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elsif (twi_clk_phase(1) = '1') then
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twi_sda_o <= '0';
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twi_sda_o <= '0';
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end if;
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end if;
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--
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_scl_o <= '1';
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twi_scl_o <= '1';
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elsif (twi_clk_phase(3) = '1') then
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elsif (twi_clk_phase(3) = '1') then
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twi_scl_o <= '0';
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twi_scl_o <= '0';
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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Line 238... |
twi_sda_o <= '0';
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twi_sda_o <= '0';
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elsif (twi_clk_phase(3) = '1') then
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elsif (twi_clk_phase(3) = '1') then
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twi_sda_o <= '1';
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twi_sda_o <= '1';
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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end if;
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--
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_scl_o <= '0';
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twi_scl_o <= '0';
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elsif (twi_clk_phase(1) = '1') then
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elsif (twi_clk_phase(1) = '1') then
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twi_scl_o <= '1';
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twi_scl_o <= '1';
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end if;
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end if;
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when "111" => -- TRANSMISSION: transmission in progress
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when "111" => -- TRANSMISSION: transmission in progress
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_bitcnt <= std_ulogic_vector(unsigned(twi_bitcnt) + 1);
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bitcnt <= std_ulogic_vector(unsigned(bitcnt) + 1);
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twi_scl_o <= '0';
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twi_scl_o <= '0';
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twi_sda_o <= twi_rtx_sreg(8); -- MSB first
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twi_sda_o <= rtx_sreg(8); -- MSB first
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elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe
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elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe
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twi_scl_o <= '1';
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twi_scl_o <= '1';
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elsif (twi_clk_phase(3) = '1') then
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elsif (twi_clk_phase(3) = '1') then
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twi_rtx_sreg <= twi_rtx_sreg(7 downto 0) & twi_sda_i_ff1; -- sample and shift left
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rtx_sreg <= rtx_sreg(7 downto 0) & twi_sda_i_ff1; -- sample and shift left
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twi_scl_o <= '0';
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twi_scl_o <= '0';
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end if;
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end if;
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--
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if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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if (bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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end if;
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when others => -- "0--" OFFLINE: TWI deactivated
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when others => -- "0--" OFFLINE: TWI deactivated
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twi_sda_o <= '1';
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twi_sda_o <= '1';
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twi_scl_o <= '1';
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twi_scl_o <= '1';
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arbiter <= ctrl(ctrl_twi_en_c) & "00"; -- stay here, go to idle when activated
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arbiter(1 downto 0) <= "00"; -- stay here, go to idle when activated
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end case;
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end case;
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end if;
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end if;
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end process twi_rtx_unit;
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end process twi_rtx_unit;
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