| Line 109... |
Line 109... |
signal twi_sda_in : std_ulogic;
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signal twi_sda_in : std_ulogic;
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signal twi_scl_in : std_ulogic;
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signal twi_scl_in : std_ulogic;
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signal twi_sda_out : std_ulogic;
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signal twi_sda_out : std_ulogic;
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signal twi_scl_out : std_ulogic;
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signal twi_scl_out : std_ulogic;
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-- interrupt generator --
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type irq_t is record
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pending : std_ulogic; -- pending interrupt request
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set : std_ulogic;
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clr : std_ulogic;
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end record;
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signal irq : irq_t;
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0';
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| Line 196... |
Line 188... |
-- input synchronizer & sampler --
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-- input synchronizer & sampler --
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twi_sda_in_ff <= twi_sda_in_ff(0) & twi_sda_in;
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twi_sda_in_ff <= twi_sda_in_ff(0) & twi_sda_in;
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twi_scl_in_ff <= twi_scl_in_ff(0) & twi_scl_in;
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twi_scl_in_ff <= twi_scl_in_ff(0) & twi_scl_in;
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-- defaults --
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-- defaults --
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irq.set <= '0';
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irq_o <= '0';
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-- serial engine --
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-- serial engine --
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arbiter(2) <= ctrl(ctrl_en_c); -- still activated?
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arbiter(2) <= ctrl(ctrl_en_c); -- still activated?
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case arbiter is
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case arbiter is
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| Line 230... |
Line 222... |
--
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--
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_scl_out <= '1';
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twi_scl_out <= '1';
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elsif (twi_clk_phase(3) = '1') then
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elsif (twi_clk_phase(3) = '1') then
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twi_scl_out <= '0';
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twi_scl_out <= '0';
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irq.set <= '1'; -- Interrupt!
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irq_o <= '1'; -- Interrupt!
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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end if;
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when "110" => -- STOP: generate STOP condition
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when "110" => -- STOP: generate STOP condition
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_sda_out <= '0';
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twi_sda_out <= '0';
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elsif (twi_clk_phase(3) = '1') then
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elsif (twi_clk_phase(3) = '1') then
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twi_sda_out <= '1';
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twi_sda_out <= '1';
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irq.set <= '1'; -- Interrupt!
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irq_o <= '1'; -- Interrupt!
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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end if;
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--
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--
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if (twi_clk_phase(0) = '1') then
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if (twi_clk_phase(0) = '1') then
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twi_scl_out <= '0';
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twi_scl_out <= '0';
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| Line 262... |
Line 254... |
rtx_sreg <= rtx_sreg(7 downto 0) & twi_sda_in_ff(twi_sda_in_ff'left); -- sample and shift left
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rtx_sreg <= rtx_sreg(7 downto 0) & twi_sda_in_ff(twi_sda_in_ff'left); -- sample and shift left
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twi_scl_out <= '0';
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twi_scl_out <= '0';
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end if;
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end if;
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--
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--
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if (bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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if (bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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irq.set <= '1'; -- Interrupt!
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irq_o <= '1'; -- Interrupt!
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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end if;
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when others => -- "0--" OFFLINE: TWI deactivated
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when others => -- "0--" OFFLINE: TWI deactivated
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twi_sda_out <= '1';
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twi_sda_out <= '1';
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| Line 293... |
Line 285... |
-- read-back --
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-- read-back --
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twi_sda_in <= std_ulogic(twi_sda_io);
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twi_sda_in <= std_ulogic(twi_sda_io);
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twi_scl_in <= std_ulogic(twi_scl_io);
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twi_scl_in <= std_ulogic(twi_scl_io);
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-- Interrupt Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_generator: process(clk_i)
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begin
|
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if rising_edge(clk_i) then
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if (ctrl(ctrl_en_c) = '0') then
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irq.pending <= '0';
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else
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if (irq.set = '1') then
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irq.pending <= '1';
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elsif (irq.clr = '1') then
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irq.pending <= '0';
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end if;
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end if;
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end if;
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end process irq_generator;
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-- IRQ request to CPU --
|
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irq_o <= irq.pending;
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-- IRQ acknowledge --
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irq.clr <= '1' when ((rden = '1') and (addr = twi_rtx_addr_c)) or (wren = '1') else '0'; -- read data register OR write data/control register
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end neorv32_twi_rtl;
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end neorv32_twi_rtl;
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No newline at end of file
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No newline at end of file
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