| Line 26... |
Line 26... |
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
|
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
|
-- # No interrupts are triggered when in SIMULATION MODE. #
|
-- # No interrupts are triggered when in SIMULATION MODE. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 590... |
Line 590... |
irq_rxd_o <= '1' when (rx_irq.buf = "01") else '0';
|
irq_rxd_o <= '1' when (rx_irq.buf = "01") else '0';
|
|
|
|
|
-- SIMULATION Transmitter -----------------------------------------------------------------
|
-- SIMULATION Transmitter -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- pragma translate_off
|
simulation_transmitter:
|
-- synthesis translate_off
|
if (is_simulation_c = true) generate -- for SIMULATION ONLY!
|
-- RTL_SYNTHESIS OFF
|
sim_output: process(clk_i)
|
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
|
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
variable char_v : integer;
|
variable char_v : integer;
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
variable line_text_v : line;
|
variable line_text_v : line;
|
| Line 639... |
Line 638... |
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sim_output;
|
end process sim_output;
|
-- RTL_SYNTHESIS ON
|
end generate;
|
-- synthesis translate_on
|
|
-- pragma translate_on
|
|
|
|
end neorv32_uart_rtl;
|
end neorv32_uart_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
