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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_uart.vhd] - Diff between revs 2 and 22
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| Rev 2 |
Rev 22 |
| Line 48... |
Line 48... |
-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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| Line 144... |
Line 143... |
if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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-- write access --
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-- write access --
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if (wr_en = '1') then
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if (wr_en = '1') then
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if (addr = uart_ctrl_addr_c) then
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if (addr = uart_ctrl_addr_c) then
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for i in 0 to 3 loop
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ctrl <= data_i;
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if (ben_i(i) = '1') then
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ctrl(7+i*8 downto 0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end loop; -- i
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rd_en = '1') then
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if (rd_en = '1') then
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