| Line 2... |
Line 2... |
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> #
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-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Fixed frame config: 8-bit, no parity bit, 1 stop bit, programmable BAUD rate (via clock pre- #
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-- # Fixed frame config: 8-bit, no parity bit, 1 stop bit, programmable BAUD rate (via clock pre- #
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-- # scaler and BAUD value config register. #
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-- # scaler and BAUD value config register. #
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-- # Interrupt: UART_RX_available or UART_TX_done #
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-- # Interrupt: UART_RX_available or UART_TX_done #
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-- # #
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-- # SIMULATION: #
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-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write #
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-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
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-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
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-- # ASCII char to the simulator console. This char is also stored to a text file #
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-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char #
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-- # encoded value to text file "neorv32.uart.sim_mode.data.out". #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 40... |
Line 48... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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use std.textio.all; -- obviously only for simulation
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|
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entity neorv32_uart is
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entity neorv32_uart is
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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| Line 64... |
Line 73... |
);
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);
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end neorv32_uart;
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end neorv32_uart;
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architecture neorv32_uart_rtl of neorv32_uart is
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architecture neorv32_uart_rtl of neorv32_uart is
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-- simulation output configuration --
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constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
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constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled
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constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled
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|
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-- IO space: module base address --
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
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|
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-- accessible regs --
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-- accessible regs --
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| Line 86... |
Line 100... |
constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8
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constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8
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constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
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constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
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constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
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constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
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constant ctrl_uart_baud11_c : natural := 11; -- r/w: UART baud config bit 11
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constant ctrl_uart_baud11_c : natural := 11; -- r/w: UART baud config bit 11
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--
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--
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constant ctrl_uart_sim_en_c : natural := 12; -- r/w: UART SIMULATION OUTPUT enable
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--
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constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
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constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
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constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
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constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
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constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
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constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
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constant ctrl_uart_rxovr_c : natural := 27; -- r/-: UART RX overrun
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constant ctrl_uart_rxovr_c : natural := 27; -- r/-: UART RX overrun
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constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
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constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
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| Line 178... |
Line 194... |
uart_tx_unit: process(clk_i)
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uart_tx_unit: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- serial engine --
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-- serial engine --
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uart_tx_done <= '0';
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uart_tx_done <= '0';
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if (uart_tx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
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if (uart_tx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
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uart_tx_busy <= '0';
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uart_tx_busy <= '0';
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uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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uart_tx_bitcnt <= "1010"; -- 10 bit
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uart_tx_bitcnt <= "1010"; -- 10 bit
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if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) then
|
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
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uart_tx_sreg <= '1' & data_i(7 downto 0) & '0'; -- stopbit & data & startbit
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uart_tx_sreg <= '1' & data_i(7 downto 0) & '0'; -- stopbit & data & startbit
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uart_tx_busy <= '1';
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uart_tx_busy <= '1';
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end if;
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end if;
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elsif (uart_clk = '1') then
|
elsif (uart_clk = '1') then
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if (uart_tx_baud_cnt = x"000") then
|
if (uart_tx_baud_cnt = x"000") then
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| Line 254... |
Line 270... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- UART Rx data available [OR] UART Tx complete
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-- UART Rx data available [OR] UART Tx complete
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uart_irq_o <= (uart_rx_busy_ff and (not uart_rx_busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx_done and ctrl(ctrl_uart_tx_irq_c));
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uart_irq_o <= (uart_rx_busy_ff and (not uart_rx_busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx_done and ctrl(ctrl_uart_tx_irq_c));
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|
|
|
|
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-- SIMULATION Output ----------------------------------------------------------------------
|
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-- -------------------------------------------------------------------------------------------
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sim_output: process(clk_i) -- for SIMULATION ONLY!
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file file_devnull_text_out : text open write_mode is "neorv32.uart.sim_mode.text.out";
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file file_devnull_data_out : text open write_mode is "neorv32.uart.sim_mode.data.out";
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variable char_v : integer;
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variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
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variable line_text_v : line;
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variable line_data_v : line;
|
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begin
|
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if rising_edge(clk_i) then
|
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if (ctrl(ctrl_uart_en_c) = '1') and (ctrl(ctrl_uart_sim_en_c) = '1') then -- UART enabled and simulation output selected?
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if (wr_en = '1') and (addr = uart_rtx_addr_c) then -- write access to tx register
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|
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-- print lowest byte to ASCII char --
|
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char_v := to_integer(unsigned(data_i(7 downto 0)));
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if (char_v >= 128) then -- out of range?
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char_v := 0;
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end if;
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|
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if (char_v /= 10) and (char_v /= 13) then -- skip line breaks - they are issued via "writeline"
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if (sim_screen_output_en_c = true) then
|
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write(line_screen_v, character'val(char_v));
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end if;
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if (sim_text_output_en_c = true) then
|
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write(line_text_v, character'val(char_v));
|
|
end if;
|
|
end if;
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|
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if (char_v = 10) then -- line break: write to screen and text file
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if (sim_screen_output_en_c = true) then
|
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writeline(output, line_screen_v);
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end if;
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if (sim_text_output_en_c = true) then
|
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writeline(file_devnull_text_out, line_text_v);
|
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end if;
|
|
end if;
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|
|
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-- dump raw data as 8 hex char text to file --
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if (sim_data_output_en_c = true) then
|
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for x in 7 downto 0 loop
|
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write(line_data_v, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form
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|
end loop; -- x
|
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writeline(file_devnull_data_out, line_data_v);
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end if;
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|
|
end if;
|
|
end if;
|
|
end if;
|
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end process sim_output;
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|
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|
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end neorv32_uart_rtl;
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end neorv32_uart_rtl;
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No newline at end of file
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No newline at end of file
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