| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> #
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-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, #
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-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, #
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-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. #
|
-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. #
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-- # Interrupt: UART_RX_available or UART_TX_done #
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-- # Interrupt: UART_RX_available or UART_TX_done #
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-- # #
|
-- # #
|
|
-- # UART0 / UART1: #
|
|
-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the #
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|
-- # interface register addresses and simulation output setting for UART0 (UART_PRIMARY = true) #
|
|
-- # or UART1 (UART_PRIMARY = false). #
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|
-- # #
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-- # SIMULATION: #
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-- # SIMULATION: #
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-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write #
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-- # When the simulation mode is enabled (setting the ctrl.ctrl_uart_sim_en_c bit) any write #
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-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
|
-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
|
-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
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-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
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-- # ASCII char to the simulator console. This char is also stored to a text file #
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-- # ASCII char to the simulator console. #
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-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char #
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-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 #
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-- # encoded value to text file "neorv32.uart.sim_mode.data.out". #
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-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value #
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|
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 51... |
Line 57... |
library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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use std.textio.all; -- obviously only for simulation
|
use std.textio.all; -- obviously only for simulation
|
|
|
entity neorv32_uart is
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entity neorv32_uart is
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|
generic (
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|
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
);
|
port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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| Line 74... |
Line 83... |
);
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);
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end neorv32_uart;
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end neorv32_uart;
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|
architecture neorv32_uart_rtl of neorv32_uart is
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architecture neorv32_uart_rtl of neorv32_uart is
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|
|
|
-- interface configuration for UART0 / UART1 --
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|
constant uart_id_base_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c);
|
|
constant uart_id_size_c : natural := cond_sel_natural_f( UART_PRIMARY, uart0_size_c, uart1_size_c);
|
|
constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c);
|
|
constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c);
|
|
|
|
-- IO space: module base address --
|
|
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
|
|
constant lo_abb_c : natural := index_size_f(uart_id_size_c); -- low address boundary bit
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|
|
-- simulation output configuration --
|
-- simulation output configuration --
|
constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
|
constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
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constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled
|
constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled
|
constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled
|
constant sim_data_output_en_c : boolean := true; -- dump 32-word to file when enabled
|
|
|
-- IO space: module base address --
|
-- simulation output file configuration --
|
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
|
constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out");
|
constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
|
constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out");
|
|
|
-- accessible regs --
|
-- accessible regs --
|
signal ctrl : std_ulogic_vector(31 downto 0);
|
signal ctrl : std_ulogic_vector(31 downto 0);
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|
|
-- control reg bits --
|
-- control reg bits --
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| Line 95... |
Line 114... |
constant ctrl_uart_baud03_c : natural := 3; -- r/w: UART baud config bit 3
|
constant ctrl_uart_baud03_c : natural := 3; -- r/w: UART baud config bit 3
|
constant ctrl_uart_baud04_c : natural := 4; -- r/w: UART baud config bit 4
|
constant ctrl_uart_baud04_c : natural := 4; -- r/w: UART baud config bit 4
|
constant ctrl_uart_baud05_c : natural := 5; -- r/w: UART baud config bit 5
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constant ctrl_uart_baud05_c : natural := 5; -- r/w: UART baud config bit 5
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constant ctrl_uart_baud06_c : natural := 6; -- r/w: UART baud config bit 6
|
constant ctrl_uart_baud06_c : natural := 6; -- r/w: UART baud config bit 6
|
constant ctrl_uart_baud07_c : natural := 7; -- r/w: UART baud config bit 7
|
constant ctrl_uart_baud07_c : natural := 7; -- r/w: UART baud config bit 7
|
--
|
|
constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8
|
constant ctrl_uart_baud08_c : natural := 8; -- r/w: UART baud config bit 8
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constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
|
constant ctrl_uart_baud09_c : natural := 9; -- r/w: UART baud config bit 9
|
constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
|
constant ctrl_uart_baud10_c : natural := 10; -- r/w: UART baud config bit 10
|
constant ctrl_uart_baud11_c : natural := 11; -- r/w: UART baud config bit 11
|
constant ctrl_uart_baud11_c : natural := 11; -- r/w: UART baud config bit 11
|
--
|
--
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| Line 159... |
Line 177... |
|
|
begin
|
begin
|
|
|
-- Access Control -------------------------------------------------------------------------
|
-- Access Control -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_id_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
addr <= uart_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
|
addr <= uart_id_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
|
wr_en <= acc_en and wren_i;
|
wr_en <= acc_en and wren_i;
|
rd_en <= acc_en and rden_i;
|
rd_en <= acc_en and rden_i;
|
|
|
|
|
-- Read/Write Access ----------------------------------------------------------------------
|
-- Read/Write Access ----------------------------------------------------------------------
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| Line 173... |
Line 191... |
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
ack_o <= acc_en and (rden_i or wren_i);
|
ack_o <= acc_en and (rden_i or wren_i);
|
-- write access --
|
-- write access --
|
if (wr_en = '1') then
|
if (wr_en = '1') then
|
if (addr = uart_ctrl_addr_c) then
|
if (addr = uart_id_ctrl_addr_c) then
|
ctrl <= (others => '0');
|
ctrl <= (others => '0');
|
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
|
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
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ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
|
ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
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ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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| Line 185... |
Line 203... |
end if;
|
end if;
|
end if;
|
end if;
|
-- read access --
|
-- read access --
|
data_o <= (others => '0');
|
data_o <= (others => '0');
|
if (rd_en = '1') then
|
if (rd_en = '1') then
|
if (addr = uart_ctrl_addr_c) then
|
if (addr = uart_id_ctrl_addr_c) then
|
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
|
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
|
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
|
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
|
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
|
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
|
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
|
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
|
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
|
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
|
else -- uart_rtx_addr_c
|
else -- uart_id_rtx_addr_c
|
data_o(data_rx_avail_c) <= uart_rx.avail(0);
|
data_o(data_rx_avail_c) <= uart_rx.avail(0);
|
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
|
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
|
data_o(data_rx_ferr_c) <= uart_rx.ferr;
|
data_o(data_rx_ferr_c) <= uart_rx.ferr;
|
data_o(data_rx_perr_c) <= uart_rx.perr;
|
data_o(data_rx_perr_c) <= uart_rx.perr;
|
data_o(07 downto 0) <= uart_rx.data;
|
data_o(07 downto 0) <= uart_rx.data;
|
| Line 230... |
Line 248... |
if (uart_tx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
|
if (uart_tx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
|
uart_tx.busy <= '0';
|
uart_tx.busy <= '0';
|
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
|
uart_tx.bitcnt <= num_bits;
|
uart_tx.bitcnt <= num_bits;
|
uart_tx.sreg(0) <= '1';
|
uart_tx.sreg(0) <= '1';
|
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
|
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
|
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
|
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
|
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
|
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
|
else
|
else
|
uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
|
uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
|
end if;
|
end if;
|
| Line 299... |
Line 317... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- RX available flag --
|
-- RX available flag --
|
uart_rx.busy_ff <= uart_rx.busy;
|
uart_rx.busy_ff <= uart_rx.busy;
|
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then -- off/RX read access
|
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_id_rtx_addr_c)) then -- off/RX read access
|
uart_rx.avail <= "00";
|
uart_rx.avail <= "00";
|
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done
|
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done
|
uart_rx.avail <= uart_rx.avail(0) & '1';
|
uart_rx.avail <= uart_rx.avail(0) & '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 319... |
Line 337... |
|
|
|
|
-- SIMULATION Output ----------------------------------------------------------------------
|
-- SIMULATION Output ----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
file file_devnull_text_out : text open write_mode is "neorv32.uart.sim_mode.text.out";
|
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
file file_devnull_data_out : text open write_mode is "neorv32.uart.sim_mode.data.out";
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
variable char_v : integer;
|
variable char_v : integer;
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
variable line_text_v : line;
|
variable line_text_v : line;
|
variable line_data_v : line;
|
variable line_data_v : line;
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl(ctrl_uart_en_c) = '1') and (ctrl(ctrl_uart_sim_en_c) = '1') then -- UART enabled and simulation output selected?
|
if (ctrl(ctrl_uart_en_c) = '1') and (ctrl(ctrl_uart_sim_en_c) = '1') then -- UART enabled and simulation output selected?
|
if (wr_en = '1') and (addr = uart_rtx_addr_c) then -- write access to tx register
|
if (wr_en = '1') and (addr = uart_id_rtx_addr_c) then -- write access to tx register
|
|
|
-- print lowest byte to ASCII char --
|
-- print lowest byte to ASCII char --
|
char_v := to_integer(unsigned(data_i(7 downto 0)));
|
char_v := to_integer(unsigned(data_i(7 downto 0)));
|
if (char_v >= 128) then -- out of range?
|
if (char_v >= 128) then -- out of range?
|
char_v := 0;
|
char_v := 0;
|
| Line 350... |
Line 368... |
if (char_v = 10) then -- line break: write to screen and text file
|
if (char_v = 10) then -- line break: write to screen and text file
|
if (sim_screen_output_en_c = true) then
|
if (sim_screen_output_en_c = true) then
|
writeline(output, line_screen_v);
|
writeline(output, line_screen_v);
|
end if;
|
end if;
|
if (sim_text_output_en_c = true) then
|
if (sim_text_output_en_c = true) then
|
writeline(file_devnull_text_out, line_text_v);
|
writeline(file_uart_text_out, line_text_v);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- dump raw data as 8 hex char text to file --
|
-- dump raw data as 8 hex char text to file --
|
if (sim_data_output_en_c = true) then
|
if (sim_data_output_en_c = true) then
|
for x in 7 downto 0 loop
|
for x in 7 downto 0 loop
|
write(line_data_v, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form
|
write(line_data_v, to_hexchar_f(data_i(3+x*4 downto 0+x*4))); -- write in hex form
|
end loop; -- x
|
end loop; -- x
|
writeline(file_devnull_data_out, line_data_v);
|
writeline(file_uart_data_out, line_data_v);
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
