URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_uart.vhd] - Diff between revs 51 and 56
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 51 |
Rev 56 |
| Line 401... |
Line 401... |
irq_txd_o <= uart_tx.done;
|
irq_txd_o <= uart_tx.done;
|
|
|
|
|
-- SIMULATION Output ----------------------------------------------------------------------
|
-- SIMULATION Output ----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
-- pragma translate_off
|
|
-- synthesis translate_off
|
|
-- RTL_SYNTHESIS OFF
|
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
variable char_v : integer;
|
variable char_v : integer;
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
| Line 449... |
Line 452... |
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sim_output;
|
end process sim_output;
|
|
-- RTL_SYNTHESIS ON
|
|
-- synthesis translate_on
|
|
-- pragma translate_on
|
|
|
end neorv32_uart_rtl;
|
end neorv32_uart_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.