| Line 239... |
Line 239... |
data_o(ctrl_uart_cts_en_c) <= ctrl(ctrl_uart_cts_en_c);
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data_o(ctrl_uart_cts_en_c) <= ctrl(ctrl_uart_cts_en_c);
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data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
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data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
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data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
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data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
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data_o(ctrl_uart_cts_c) <= uart_cts_ff(1);
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data_o(ctrl_uart_cts_c) <= uart_cts_ff(1);
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else -- uart_id_rtx_addr_c
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else -- uart_id_rtx_addr_c
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data_o(data_rx_avail_c) <= or_all_f(uart_rx.avail);
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data_o(data_rx_avail_c) <= or_reduce_f(uart_rx.avail);
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data_o(data_rx_overr_c) <= and_all_f(uart_rx.avail);
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data_o(data_rx_overr_c) <= and_reduce_f(uart_rx.avail);
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data_o(data_rx_ferr_c) <= uart_rx.ferr_rd;
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data_o(data_rx_ferr_c) <= uart_rx.ferr_rd;
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data_o(data_rx_perr_c) <= uart_rx.perr_rd;
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data_o(data_rx_perr_c) <= uart_rx.perr_rd;
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data_o(7 downto 0) <= uart_rx.data_rd;
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data_o(7 downto 0) <= uart_rx.data_rd;
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end if;
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end if;
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end if;
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end if;
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| Line 278... |
Line 278... |
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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uart_tx.bitcnt <= num_bits;
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uart_tx.bitcnt <= num_bits;
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uart_tx.sreg(0) <= '1';
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uart_tx.sreg(0) <= '1';
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if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
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if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_id_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
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if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
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if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
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uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
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uart_tx.sreg <= '1' & (xor_reduce_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
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else
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else
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uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
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uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
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end if;
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end if;
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uart_tx.busy <= '1';
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uart_tx.busy <= '1';
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end if;
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end if;
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| Line 342... |
Line 342... |
uart_rx.baud_cnt <= std_ulogic_vector(unsigned(uart_rx.baud_cnt) - 1);
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uart_rx.baud_cnt <= std_ulogic_vector(unsigned(uart_rx.baud_cnt) - 1);
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end if;
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end if;
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if (uart_rx.bitcnt = "0000") then
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if (uart_rx.bitcnt = "0000") then
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uart_rx.busy <= '0'; -- done
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uart_rx.busy <= '0'; -- done
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-- data buffer (double buffering) --
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-- data buffer (double buffering) --
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uart_rx.perr(0) <= ctrl(ctrl_uart_pmode1_c) and (xor_all_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
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uart_rx.perr(0) <= ctrl(ctrl_uart_pmode1_c) and (xor_reduce_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
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uart_rx.ferr(0) <= not uart_rx.sreg(9); -- check stop bit (error if not set)
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uart_rx.ferr(0) <= not uart_rx.sreg(9); -- check stop bit (error if not set)
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if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
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if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
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uart_rx.data(0) <= uart_rx.sreg(7 downto 0);
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uart_rx.data(0) <= uart_rx.sreg(7 downto 0);
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else
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else
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uart_rx.data(0) <= uart_rx.sreg(8 downto 1);
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uart_rx.data(0) <= uart_rx.sreg(8 downto 1);
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