Subversion Repositories neorv32

-- # The internal counter is 20 bit wide and increases using 1 out of 8 available clock            #

-- # Watchdog counter to trigger an action if the CPU gets stuck.                                  #

-- # prescalers. When the counter overflows, either a hardware reset (mode = 1) is performed or an #

-- # The internal counter is 20-bit wide. If this counter overflows one of two possible actions is #

-- # interrupt (mode = 0) is triggered. The WDT can only operate when the enable bit is set. A     #

-- # triggered: Generate an IRQ or force a hardware reset of the system.                           #

-- # write access to the WDT can only be performed, if the higher byte of the written data         #

-- # A WDT action can also be triggered manually at any time by setting the FORCE bit.             #

-- # contains the specific WDT password (0x47). For a write access with a wrong password           #

-- #                                                                                               #

-- # a HW reset or IRQ (depending on mode) is triggered, but only if the WDT is enabled.           #

-- # Access to the control register can be permanently locked by setting the lock bit. This bit    #

  constant ctrl_clksel0_c : natural := 0; -- r/w: prescaler select bit 0

  constant ctrl_enable_c  : natural := 0; -- r/w: WDT enable

  constant ctrl_clksel1_c : natural := 1; -- r/w: prescaler select bit 1

  constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0

  constant ctrl_clksel2_c : natural := 2; -- r/w: prescaler select bit 2

  constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1

  constant ctrl_enable_c  : natural := 3; -- r/w: WDT enable

  constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2

  constant ctrl_mode_c    : natural := 4; -- r/w: 0: timeout causes interrupt, 1: timeout causes hard reset

  constant ctrl_mode_c    : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset

  constant ctrl_cause_c   : natural := 5; -- r/-: action (reset/IRQ) cause (0: external, 1: watchdog)

  constant ctrl_rcause_c  : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow

  constant ctrl_pwfail_c  : natural := 6; -- r/-: watchdog action (reset/IRQ) caused by wrong password access when '1'

  constant ctrl_reset_c   : natural := 6; -- -/w: reset WDT if set

  -- accessible regs --

  -- control register --

  signal source  : std_ulogic; -- source of wdt action: '0' = external, '1' = watchdog

  type ctrl_reg_t is record

  signal pw_fail : std_ulogic; -- watchdog action caused by wrong password access

    enable  : std_ulogic; -- 1=WDT enabled

  signal enable  : std_ulogic;

    clk_sel : std_ulogic_vector(2 downto 0);

  signal mode    : std_ulogic;

    mode    : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow

  signal clk_sel : std_ulogic_vector(02 downto 0);

    rcause  : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog

    reset   : std_ulogic; -- reset WDT

  -- reset counter --

    force   : std_ulogic; -- force action

  signal cnt      : std_ulogic_vector(20 downto 0);

    lock    : std_ulogic; -- lock control register

  signal rst_gen  : std_ulogic_vector(03 downto 0);

  end record;

  signal rst_sync : std_ulogic_vector(01 downto 0);

  signal ctrl_reg : ctrl_reg_t;

  pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check

  wren   <= acc_en and wren_i;

  wren   <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok

  rden   <= acc_en and rden_i;

  -- Write Access, Reset Generator ----------------------------------------------------------

  -- Write Access ---------------------------------------------------------------------------

  wdt_core: process(clk_i)

  write_access: process(rstn_i, clk_i)

    if rising_edge(clk_i) then

    if (rstn_i = '0') then

      if (rstn_i = '0') or (rst_sync(1) = '0') then -- external or internal reset

      ctrl_reg.reset   <= '0';

        enable  <= '0'; -- disable WDT

      ctrl_reg.force   <= '0';

        mode    <= '0'; -- trigger interrupt if watchdog timeouts

      ctrl_reg.enable  <= '0'; -- disable WDT

        clk_sel <= (others => '1'); -- slowest clock rst_source

      ctrl_reg.mode    <= '0'; -- trigger interrupt on WDT overflow

        rst_gen <= (others => '1'); -- do NOT fire on reset!

      ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source

        -- control register write access --

        -- auto-clear WDT reset and WDT force flags --

        if (wren = '1') then -- allow write if password is correct

        ctrl_reg.reset <= '0';

          enable  <= data_i(ctrl_enable_c);

        ctrl_reg.force <= '0';

          clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);

        -- actual write access --

          mode    <= data_i(ctrl_mode_c);

        if (wren = '1') then

  end process wdt_core;

  end process write_access;

  -- enable external clock generator --

  -- clock generator --

  clkgen_en_o <= enable;

  clkgen_en_o <= ctrl_reg.enable; -- enable clock generator

  -- Counter Update -------------------------------------------------------------------------

  -- Watchdog Counter -----------------------------------------------------------------------

  cnt_sync: process(clk_i)

  wdt_counter: process(clk_i)

      -- clock_en buffer --

      if (ctrl_reg.reset = '1') then -- watchdog reset

      prsc_tick <= clkgen_i(to_integer(unsigned(clk_sel)));

        wdt_cnt <= (others => '0');

      -- unauthorized access buffer --

      elsif (ctrl_reg.enable = '1') and (prsc_tick = '1') then

      fail_ff <= fail;

        wdt_cnt <= std_ulogic_vector(unsigned(wdt_cnt) + 1);

  end process cnt_sync;

  end process wdt_counter;

  -- system reset --

  -- action trigger --

  rstn_o <= rst_sync(1);

  irq_o  <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.force) and (not ctrl_reg.mode); -- mode 0: IRQ

  -- Reset Cause Indicator ------------------------------------------------------------------

  -- Reset Generator & Action Cause Indicator -----------------------------------------------

  rst_cause: process(rstn_i, clk_i)

  reset_generator: process(rstn_i, clk_i)

      source  <= '0';

      ctrl_reg.rcause <= '0';

      pw_fail <= '0';

      rst_gen         <= (others => '1'); -- do NOT fire on reset!

      source  <= source or (cnt(cnt'left) and enable) or (fail_ff and enable); -- set on WDT timeout or access error

      ctrl_reg.rcause <= ctrl_reg.rcause or hw_rst; -- sticky-set on WDT timeout/force

      pw_fail <= (pw_fail or (fail_ff and enable)) and (not (cnt(cnt'left) and enable)); -- set on failed access, clear on WDT timeout

      if (hw_rst = '1') then

  end process rst_cause;

  end process reset_generator;

      ack_o  <= acc_en and (rden_i or wren_i);

      ack_o  <= rden or wren;