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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_wdt.vhd] - Diff between revs 65 and 68
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| Rev 65 |
Rev 68 |
| Line 138... |
Line 138... |
ctrl_reg.enforce <= '0';
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ctrl_reg.enforce <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl_reg.lock <= '0';
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ctrl_reg.lock <= '0';
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cpu_irq.clr <= '-';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- acknowledge interrupt when resetting WDT --
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-- acknowledge interrupt when resetting WDT --
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cpu_irq.clr <= ctrl_reg.reset;
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if (rstn_sync = '0') then -- internal reset
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if (rstn_sync = '0') then -- internal reset
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ctrl_reg.reset <= '0';
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ctrl_reg.reset <= '0';
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ctrl_reg.enforce <= '0';
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ctrl_reg.enforce <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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| Line 188... |
Line 186... |
end if;
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end if;
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end process wdt_counter;
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end process wdt_counter;
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-- action trigger --
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-- action trigger --
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cpu_irq.set <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
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cpu_irq.set <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
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cpu_irq.clr <= ctrl_reg.reset; -- ack IRQ on WDT reset
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hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
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hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
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-- Interrupt ------------------------------------------------------------------------------
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-- Interrupt ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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