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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_wdt is
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entity neorv32_wdt is
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generic (
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DEBUG_EN : boolean -- CPU debug mode implemented?
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);
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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rstn_i : in std_ulogic; -- global reset line, low-active
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- CPU in debug mode? --
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cpu_debug_i : in std_ulogic;
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- timeout event --
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-- timeout event --
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irq_o : out std_ulogic; -- timeout IRQ
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irq_o : out std_ulogic; -- timeout IRQ
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constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset
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constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset
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constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow
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constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow
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constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set
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constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set
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constant ctrl_force_c : natural := 7; -- -/w: force WDT action
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constant ctrl_force_c : natural := 7; -- -/w: force WDT action
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constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set
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constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set
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constant ctrl_dben_c : natural := 9; -- r/w: allow WDT to continue operation even when in debug mode
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constant ctrl_half_c : natural := 10; -- r/-: set if at least half of the max. timeout counter value has been reached
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal wren : std_ulogic;
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signal wren : std_ulogic;
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signal rden : std_ulogic;
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signal rden : std_ulogic;
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-- control register --
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-- control register --
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type ctrl_reg_t is record
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type ctrl_t is record
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enable : std_ulogic; -- 1=WDT enabled
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enable : std_ulogic; -- 1=WDT enabled
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clk_sel : std_ulogic_vector(2 downto 0);
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clk_sel : std_ulogic_vector(2 downto 0);
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mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow
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mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow
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rcause : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog
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rcause : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog
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reset : std_ulogic; -- reset WDT
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reset : std_ulogic; -- reset WDT
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enforce : std_ulogic; -- force action
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enforce : std_ulogic; -- force action
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lock : std_ulogic; -- lock control register
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lock : std_ulogic; -- lock control register
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dben : std_ulogic; -- allow operation also in debug mode
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end record;
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end record;
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signal ctrl_reg : ctrl_reg_t;
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signal ctrl : ctrl_t;
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-- prescaler clock generator --
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-- prescaler clock generator --
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signal prsc_tick : std_ulogic;
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signal prsc_tick : std_ulogic;
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-- WDT core --
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-- WDT core --
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signal wdt_cnt : std_ulogic_vector(20 downto 0);
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signal wdt_cnt : std_ulogic_vector(20 downto 0);
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signal hw_rst : std_ulogic;
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signal hw_rst : std_ulogic;
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signal rst_gen : std_ulogic_vector(03 downto 0);
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signal rst_gen : std_ulogic_vector(03 downto 0);
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signal cnt_en : std_ulogic;
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-- internal reset (sync, low-active) --
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-- internal reset (sync, low-active) --
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signal rstn_sync : std_ulogic;
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signal rstn_sync : std_ulogic;
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-- cpu interrupt --
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type cpu_irq_t is record
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pending : std_ulogic;
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set : std_ulogic;
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clr : std_ulogic;
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end record;
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signal cpu_irq : cpu_irq_t;
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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write_access: process(rstn_i, clk_i)
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write_access: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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ctrl_reg.reset <= '0';
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ctrl.reset <= '1'; -- reset counter on start-up
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ctrl_reg.enforce <= '0';
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ctrl.enforce <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl.mode <= '0';
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl.clk_sel <= (others => '0');
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ctrl_reg.lock <= '0';
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ctrl.lock <= '0';
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ctrl.dben <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- acknowledge interrupt when resetting WDT --
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if (rstn_sync = '0') then -- internal reset
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if (rstn_sync = '0') then -- internal reset
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ctrl_reg.reset <= '0';
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ctrl.reset <= '1'; -- reset counter on start-up
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ctrl_reg.enforce <= '0';
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ctrl.enforce <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl.mode <= '0';
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl.clk_sel <= (others => '0');
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ctrl_reg.lock <= '0';
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ctrl.lock <= '0';
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ctrl.dben <= '0';
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else
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else
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-- auto-clear WDT reset and WDT force flags --
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-- auto-clear WDT reset and WDT force flags --
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ctrl_reg.reset <= '0';
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ctrl.reset <= '0';
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ctrl_reg.enforce <= '0';
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ctrl.enforce <= '0';
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-- actual write access --
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-- actual write access --
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if (wren = '1') then
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if (wren = '1') then
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ctrl_reg.reset <= data_i(ctrl_reset_c);
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ctrl.reset <= data_i(ctrl_reset_c);
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ctrl_reg.enforce <= data_i(ctrl_force_c);
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ctrl.enforce <= data_i(ctrl_force_c);
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if (ctrl_reg.lock = '0') then -- update configuration only if unlocked
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if (ctrl.lock = '0') then -- update configuration only if not locked
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ctrl_reg.enable <= data_i(ctrl_enable_c);
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ctrl.enable <= data_i(ctrl_enable_c);
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ctrl_reg.mode <= data_i(ctrl_mode_c);
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ctrl.mode <= data_i(ctrl_mode_c);
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ctrl_reg.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
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ctrl.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
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ctrl_reg.lock <= data_i(ctrl_lock_c);
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ctrl.lock <= data_i(ctrl_lock_c);
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ctrl.dben <= data_i(ctrl_dben_c) and bool_to_ulogic_f(DEBUG_EN);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process write_access;
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end process write_access;
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-- clock generator --
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-- clock generator --
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clkgen_en_o <= ctrl_reg.enable; -- enable clock generator
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clkgen_en_o <= ctrl.enable; -- enable clock generator
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prsc_tick <= clkgen_i(to_integer(unsigned(ctrl_reg.clk_sel))); -- clock enable tick
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prsc_tick <= clkgen_i(to_integer(unsigned(ctrl.clk_sel))); -- clock enable tick
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-- Watchdog Counter -----------------------------------------------------------------------
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-- Watchdog Counter -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wdt_counter: process(clk_i)
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wdt_counter: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_reg.reset = '1') then -- watchdog reset
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if (ctrl.reset = '1') then -- watchdog reset
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wdt_cnt <= (others => '0');
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wdt_cnt <= (others => '0');
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elsif (ctrl_reg.enable = '1') and (prsc_tick = '1') then
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elsif (cnt_en = '1') then
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wdt_cnt <= std_ulogic_vector(unsigned(wdt_cnt) + 1);
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wdt_cnt <= std_ulogic_vector(unsigned('0' & wdt_cnt(wdt_cnt'left-1 downto 0)) + 1);
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end if;
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end if;
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end if;
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end if;
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end process wdt_counter;
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end process wdt_counter;
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-- action trigger --
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-- WDT counter enable --
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cpu_irq.set <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
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cnt_en <= ctrl.enable and prsc_tick and ((not cpu_debug_i) or ctrl.dben);
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cpu_irq.clr <= ctrl_reg.reset; -- ack IRQ on WDT reset
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hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
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-- Interrupt ------------------------------------------------------------------------------
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-- action trigger --
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-- -------------------------------------------------------------------------------------------
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irq_o <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and (not ctrl.mode); -- mode 0: IRQ
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irq_gen: process(clk_i)
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hw_rst <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and ( ctrl.mode); -- mode 1: RESET
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begin
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if rising_edge(clk_i) then
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if (ctrl_reg.enable = '0') then
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cpu_irq.pending <= '0';
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else
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if (cpu_irq.set = '1') then
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cpu_irq.pending <= '1';
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elsif(cpu_irq.clr = '1') then
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cpu_irq.pending <= '0';
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else
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cpu_irq.pending <= cpu_irq.pending;
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end if;
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end if;
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end if;
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end process irq_gen;
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-- CPU IRQ --
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irq_o <= cpu_irq.pending;
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-- Reset Generator & Action Cause Indicator -----------------------------------------------
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-- Reset Generator & Action Cause Indicator -----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reset_generator: process(rstn_i, clk_i)
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reset_generator: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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ctrl_reg.rcause <= '0';
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ctrl.rcause <= '0';
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rst_gen <= (others => '1'); -- do NOT fire on reset!
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rst_gen <= (others => '1'); -- do NOT fire on reset!
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rstn_sync <= '1';
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rstn_sync <= '1';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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ctrl_reg.rcause <= ctrl_reg.rcause or hw_rst; -- sticky-set on WDT timeout/force
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ctrl.rcause <= ctrl.rcause or hw_rst; -- sticky-set on WDT timeout/force
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if (hw_rst = '1') then
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if (hw_rst = '1') then
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rst_gen <= (others => '0');
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rst_gen <= (others => '0');
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else
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else
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rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
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rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
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end if;
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end if;
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Line 225... |
read_access: process(clk_i)
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read_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= rden or wren;
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ack_o <= rden or wren;
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if (rden = '1') then
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if (rden = '1') then
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data_o(ctrl_enable_c) <= ctrl_reg.enable;
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data_o(ctrl_enable_c) <= ctrl.enable;
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data_o(ctrl_mode_c) <= ctrl_reg.mode;
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data_o(ctrl_mode_c) <= ctrl.mode;
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data_o(ctrl_rcause_c) <= ctrl_reg.rcause;
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data_o(ctrl_rcause_c) <= ctrl.rcause;
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data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl_reg.clk_sel;
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data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_sel;
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data_o(ctrl_lock_c) <= ctrl_reg.lock;
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data_o(ctrl_lock_c) <= ctrl.lock;
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data_o(ctrl_dben_c) <= ctrl.dben;
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data_o(ctrl_half_c) <= wdt_cnt(wdt_cnt'left-1);
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else
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else
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data_o <= (others => '0');
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data_o <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process read_access;
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end process read_access;
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