| Line 75... |
Line 75... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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lock_i : in std_ulogic; -- exclusive access request
|
lock_i : in std_ulogic; -- exclusive access request
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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tmo_o : out std_ulogic; -- transfer timeout
|
tmo_o : out std_ulogic; -- transfer timeout
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
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priv_i : in std_ulogic; -- current CPU privilege level
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ext_o : out std_ulogic; -- active external access
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ext_o : out std_ulogic; -- active external access
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-- xip configuration --
|
-- xip configuration --
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xip_en_i : in std_ulogic; -- XIP module enabled
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xip_en_i : in std_ulogic; -- XIP module enabled
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xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
|
xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
|
-- wishbone interface --
|
-- wishbone interface --
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| Line 123... |
Line 123... |
err : std_ulogic;
|
err : std_ulogic;
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tmo : std_ulogic;
|
tmo : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0);
|
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0);
|
src : std_ulogic;
|
src : std_ulogic;
|
lock : std_ulogic;
|
lock : std_ulogic;
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priv : std_ulogic_vector(01 downto 0);
|
priv : std_ulogic;
|
end record;
|
end record;
|
signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
|
signal stb_int : std_ulogic;
|
signal stb_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
signal rdata : std_ulogic_vector(31 downto 0);
|
signal rdata : std_ulogic_vector(31 downto 0);
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| Line 186... |
Line 186... |
ctrl.ack <= def_rst_val_c;
|
ctrl.ack <= def_rst_val_c;
|
ctrl.err <= def_rst_val_c;
|
ctrl.err <= def_rst_val_c;
|
ctrl.tmo <= def_rst_val_c;
|
ctrl.tmo <= def_rst_val_c;
|
ctrl.src <= def_rst_val_c;
|
ctrl.src <= def_rst_val_c;
|
ctrl.lock <= def_rst_val_c;
|
ctrl.lock <= def_rst_val_c;
|
ctrl.priv <= (others => def_rst_val_c);
|
ctrl.priv <= def_rst_val_c;
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- defaults --
|
-- defaults --
|
ctrl.state_ff <= ctrl.state;
|
ctrl.state_ff <= ctrl.state;
|
ctrl.rdat <= (others => '0'); -- required for internal output gating
|
ctrl.rdat <= (others => '0'); -- required for internal output gating
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
