| Line 70... |
Line 70... |
rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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cancel_i : in std_ulogic; -- cancel current bus transaction
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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-- wishbone interface --
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-- wishbone interface --
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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| Line 106... |
Line 107... |
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-- Sanity Check ---------------------------------------------------------------------------
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-- Sanity Check ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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sanity_check: process(clk_i)
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sanity_check: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- just for simulation
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if rising_edge(clk_i) then
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if (INTERFACE_REG_STAGES > 2) then
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if (INTERFACE_REG_STAGES > 2) then
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assert false report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
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assert false report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
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end if;
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end if;
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end if;
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end if;
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end process sanity_check;
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end process sanity_check;
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| Line 142... |
Line 143... |
wb_err_ff <= '0';
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wb_err_ff <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- bus cycle --
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-- bus cycle --
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if (INTERFACE_REG_STAGES = 0) then
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if (INTERFACE_REG_STAGES = 0) then
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wb_cyc_ff <= '0'; -- unused
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wb_cyc_ff <= '0'; -- unused
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elsif (INTERFACE_REG_STAGES = 1) then
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else
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wb_cyc_ff <= wb_access and ((not wb_ack_i) or (not wb_err_i));
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wb_cyc_ff <= (wb_cyc_ff or wb_access) and ((not wb_ack_i) or (not wb_err_i)) and (not cancel_i);
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elsif (INTERFACE_REG_STAGES = 2) then
|
|
wb_cyc_ff <= wb_access and ((not wb_ack_ff) or (not wb_err_ff));
|
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end if;
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end if;
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-- bus strobe --
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-- bus strobe --
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wb_stb_ff1 <= wb_stb_ff0;
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wb_stb_ff1 <= wb_stb_ff0;
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wb_stb_ff0 <= wb_access;
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wb_stb_ff0 <= wb_access;
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-- bus ack --
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-- bus ack --
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| Line 186... |
Line 185... |
interface_reg_level_one:
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interface_reg_level_one:
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if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
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if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
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buffer_stages_one: process(clk_i)
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buffer_stages_one: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
|
if (wb_cyc_ff = '0') then
|
wb_adr_o <= addr_i;
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wb_adr_o <= addr_i;
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wb_dat_o <= data_i;
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wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i;
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wb_we_o <= wren_i;
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end if;
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end if;
|
|
end if;
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end process buffer_stages_one;
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end process buffer_stages_one;
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data_o <= wb_dat_i;
|
data_o <= wb_dat_i;
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end generate;
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end generate;
|
|
|
interface_reg_level_two:
|
interface_reg_level_two:
|
if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
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if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
|
buffer_stages_two: process(clk_i)
|
buffer_stages_two: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
|
if (wb_cyc_ff = '0') then
|
wb_adr_o <= addr_i;
|
wb_adr_o <= addr_i;
|
wb_dat_o <= data_i;
|
wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_sel_o <= ben_i;
|
wb_we_o <= wren_i;
|
wb_we_o <= wren_i;
|
data_o <= wb_dat_i;
|
data_o <= wb_dat_i;
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end if;
|
end if;
|
|
end if;
|
end process buffer_stages_two;
|
end process buffer_stages_two;
|
end generate;
|
end generate;
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|
|
|
|
end neorv32_wishbone_rtl;
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end neorv32_wishbone_rtl;
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